Renesas RL78/G10 - Noise Filter Enable Register 1 (NFEN1)

RL78/G10 CHAPTER 6 TIMER ARRAY UNIT
R01UH0384EJ0311 Rev. 3.11 133
Dec 22, 2016
6.3.12 Noise filter enable register 1 (NFEN1)
The NFEN1 register is used to set whether the noise filter can be used for the timer input (TI0n) pin signal to each
channel.
Enable the noise filter by setting the corresponding bits to 1 on the pins in need of noise removal.
When the noise filter is enabled, after synchronization with the operating clock (f
MCK) for the target channel, whether the
signal keeps the same value for two clock cycles is detected. When the noise filter is disabled, the input signal is only
synchronized with the operating clock (fMCK) for the target channel
Note
. For the timer input (TI0n) operation, see 6.5.1 (2)
When valid edge of input signal via the TI0n pin is selected (CCS0n = 1), 6.5.2 Start timing of counter, and 6.7
Timer Input (TI0n) Control.
The NFEN1 registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 6-20. Format of Noise Filter Enable Register 1 (NFEN1)
Address: F0071H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
NFEN1 0 0 0 0 TNFEN03
Note
TNFEN02
Note
TNFEN01 TNFEN00
TNFEN0n Enable/disable using noise filter of TI0n pin input signal (n = 0 to 3)
0 Noise filter OFF
1 Noise filter ON
Note 16-pin products only.
Caution The applicable pin for the noise filter set by the TNFEN01 bit can be switched by setting
the ISC1 bit in the input switch control register (ISC).
ISC1 = 0: Whether or not to use the noise filter for the TI01 pin input signal can be
selected.
ISC1 = 1: Whether or not to use the noise filter for the RxD0 pin input signal can be
selected.