RL78/G10 CHAPTER 16 STANDBY FUNCTION
R01UH0384EJ0311 Rev. 3.11 526
Dec 22, 2016
Table 16-1. Operating Statuses in HALT Mode
HALT Mode Setting
Item
When HALT Instruction Is Executed While CPU Is Operating on Main System Clock
When CPU Is Operating on High-
speed On-chip Oscillator Clock (f
IH)
When CPU Is Operating on X1
Clock (fX)
When CPU Is Operating on
External Main System Clock (fEX)
System clock Clock supply to the CPU is stopped
Main system clock fIH Operation continues
(cannot be stopped)
Operation disabled
fX Operation disabled Operation continues
(cannot be stopped)
Cannot operate
fEX Cannot operate Operation continues
(cannot be stopped)
fIL Set by bits 0 (WDSTBYON) and 4 (WDTON) of option byte (000C0H), and bit 4 (WUTMMCK0) of
operation speed mode control register (OSMC)
• WUTMMCK0 = 1: Oscillates
• WUTMMCK0 = 0 and WDTON = 0: Stops
• WUTMMCK0 = 0, WDTON = 1, and WDSTBYON = 1: Oscillates
• WUTMMCK0 = 0, WDTON = 1, and WDSTBYON = 0: Stops
CPU Operation stopped
Code flash memory
RAM
Port (latch) Status before HALT mode was set is retained
Timer array unit Operable
12-bit interval timer
Note
Watchdog timer Set by bit 0 (WDSTBYON) of option byte (000C0H)
• WDSTBYON = 0: Operation stopped
• WDSTBYON = 1: Operation continues
Clock output/buzzer output Operable
A/D converter
Comparator
Note
Serial array unit (SAU)
Serial interface (IICA)
Note
Selectable power-on-reset
function
External interrupt
Key interrupt function
Note 16-pin products only.
Remark Operation stopped: Operation is automatically stopped before switching to the HALT mode.
Operation disabled: Operation is stopped before switching to the HALT mode.
f
IH: High-speed on-chip oscillator clock
f
IL: Low-speed on-chip oscillator clock
fX: X1 clock
Note
fEX: External main system clock
Note
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