RL78/G10 CHAPTER 6 TIMER ARRAY UNIT
R01UH0384EJ0311 Rev. 3.11 116
Dec 22, 2016
Figure 6-4. Format of Timer Data Register 0n (TDR0nH, TDR0nL) (n = 0, 2)
Address: FFF18H (TDR00L), FFF19H (TDR00H), After reset: 00H R/W
FFF64H (TDR02L), FFF65H (TDR02H)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR0n
Figure 6-5. Format of Timer Data Register 0n (TDR0n) (n = 1, 3)
Address: FFF1AH (TDR01L), FFF1BH (TDR01H), After reset: 00H R/W
FFF66H (TDR03L), FFF67H (TDR03H)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR0n
(i) When timer data register 0n (TDR0nH, TDR0nL) is used as compare register
Counting down is started from the value set to the TDR0nH and TDR0nL registers. When the count value
reaches 0000H, an interrupt request signal (INTTM0n) is generated. The TDR0n register holds its value until it
is rewritten.
Caution The TDR0n register does not perform a capture operation even if a capture trigger is input,
when it is set to the compare function.
(ii) When timer data register 0n (TDR0nH, TDR0nL) is used as capture register
The count value of timer counter register 0n (TCR0n) is captured to the TDR0nH and TDR0nL registers when
the capture trigger is input.
A valid edge of the TI0n pin can be selected as the capture trigger. This selection is made by timer mode
register 0n (TMR0n).
Remark n: Channel number
n = 0, 1 (for 10-pin products); n = 0 to 3 (for 16-pin products)
FFF19H (TDR00H)
FFF18H (TDR00L)
FFF1BH (TDR01H)
FFF1AH (TDR01L)
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