RL78/G10 CHAPTER 12 SERIAL ARRAY UNIT
R01UH0384EJ0311 Rev. 3.11 361
Dec 22, 2016
Figure 12-67. Flowchart of Slave Transmission/Reception (in Continuous Transmission/Reception Mode)
Setting
transmission/reception data
Read receive data to SIOp
(=SDR0nL)
Write 1 to ST0n bit
For the initial setting, refer to Figure 12-61.
(Select buffer empty interrupt)
SAU default setting
No
Yes
No
= 1
End of communication
Yes
Yes
No
Communication
continued?
Yes
Number of communication
data
?
Disable interrupt (MASK)
BFF0n = 1?
<3>
<5>
<6>
<7>
<4>
<8>
<1>
Subtract -1 from number of
transmit data
Setting storage area and number of data for transmission/reception data
(Storage area, Transmission/reception data pointer, Number of communication data
and Communication end flag are optionally set on the internal RAM by the software)
Clea
MD0n0 bit to 0
Writing transmit data to
SIOp (=SDR0nL)
Other than the first interrupt, read reception data then writes
to storage area, update receive data pointer
If transmit data is remained, read it from storage area and write it t
SIOp. Update storage pointer.
If transmit completion (number of communication data = 1), Chang
the transmission completion interrupt
RETI
Number of communication
data
= 0?
Starting setting
Start communication when master start providing the
clock
When buffer empty/transfer end is generated, it moves
interrupt processing routine
Wait for transmission completes
Buffer empty/transfer end interrupt
≥ 2
= 0
Enables interrupt
Write 1 to MD0n0 bit
Clear interrupt request flag (XXIF), reset interrupt mask (XXMK) and set
interrupt enable (EI)
Main routine Main routineInterrupt processing routine
Caution Be sure to set transmit data to the SlOp register before the clock from the master is started.
Remark <1> to <8> in the figure correspond to <1> to <8> in Figure 12-66 Timing Chart of Slave
Transmission/Reception (in Continuous Transmission/Reception Mode).
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