RL78/G10 CHAPTER 12 SERIAL ARRAY UNIT
R01UH0384EJ0311 Rev. 3.11 314
Dec 22, 2016
(4) Processing flow (in continuous transmission mode)
Figure 12-28. Timing Chart of Master Transmission (in Continuous Transmission Mode)
(Type 1: DAP0n = 0, CKP0n = 0)
SS0n
SE0n
SDR0nL
INTCSIp
TSF0n
BFF0n
MD0n0
<1>
(Note)
ST0n
SCKp pin
SOp pin
Shift
register 0n
Transmit data 2 Transmit data 3
Transmit data 3Transmit data 2Transmit data 1
Transmit data 1
Shift operation Shift operation Shift operation
Data transmissionData transmissionData transmission
<6>
<2> <2> <2><3> <3> <3>
<4>
<5>
Note If transmit data is written to the SDR0nL register while the BFF0n bit of serial status register 0n (SSR0n) is 1
(valid data is stored in serial data register 0n (SDR0nL)), the transmit data is overwritten.
Caution The MD0n0 bit of serial mode register 0n (SMR0nH/L) can be rewritten even during operation.
However, rewrite it before transfer of the last bit is started, so that it will be rewritten before the
transfer end interrupt of the last transmit data.
Remark n = 0, 1, p: CSI number (p = 00, 01)
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