Renesas RL78/G10 User Manual

RL78/G10 CHAPTER 12 SERIAL ARRAY UNIT
R01UH0384EJ0311 Rev. 3.11 384
Dec 22, 2016
Table 12-3. Selection of Operation Clock For UART
SMR0n
Register
SPS0 Register Operation Clock (fMCK)
Note
CKS0n PRS
13
PRS
12
PRS
11
PRS
10
PRS
03
PRS
02
PRS
01
PRS
00
fCLK = 20 MHz
0 X X X X 0 0 0 0 fCLK 20 MHz
X X X X 0 0 0 1 fCLK/2 10 MHz
X X X X 0 0 1 0 fCLK/2
2
5 MHz
X X X X 0 0 1 1 fCLK/2
3
2.5 MHz
X X X X 0 1 0 0 fCLK/2
4
1.25 MHz
X X X X 0 1 0 1 fCLK/2
5
625 kHz
X X X X 0 1 1 0 fCLK/2
6
312.5 kHz
X X X X 0 1 1 1 fCLK/2
7
156.2 kHz
X X X X 1 0 0 0 fCLK/2
8
78.1 kHz
X X X X 1 0 0 1 fCLK/2
9
39.1 kHz
X X X X 1 0 1 0 fCLK/2
10
19.5 kHz
X X X X 1 0 1 1 fCLK/2
11
9.77 kHz
X X X X 1 1 0 0 fCLK/2
12
4.88 kHz
X X X X 1 1 0 1 fCLK/2
13
2.44 kHz
X X X X 1 1 1 0 fCLK/2
14
1.22 kHz
X X X X 1 1 1 1 fCLK/2
15
610 Hz
1 0 0 0 0 X X X X fCLK 20 MHz
0 0 0 1 X X X X fCLK/2 10 MHz
0 0 1 0 X X X X fCLK/2
2
5 MHz
0 0 1 1 X X X X fCLK/2
3
2.5 MHz
0 1 0 0 X X X X fCLK/2
4
1.25 MHz
0 1 0 1 X X X X fCLK/2
5
625 MHz
0 1 1 0 X X X X fCLK/2
6
312.5 kHz
0 1 1 1 X X X X fCLK/2
7
156.2 kHz
1 0 0 0 X X X X fCLK/2
8
78.1 kHz
1 0 0 1 X X X X fCLK/2
9
39.1 kHz
1 0 1 0 X X X X fCLK/2
10
19.5 kHz
1 0 1 1 X X X X fCLK/2
11
9.77 kHz
1 1 0 0 X X X X fCLK/2
12
4.88 kHz
1 1 0 1 X X X X fCLK/2
13
2.44 kHz
1 1 1 0 X X X X fCLK/2
14
1.22 kHz
1 1 1 1 X X X X fCLK/2
15
610 Hz
Note When changing the clock selected for fCLK (by changing the system clock control register (CKC) value), do so
after having stopped (serial channel stop register 0 (ST0) = 03H) the operation of the serial array unit (SAU).
Remarks 1. X: don’t care
2. n = 0, 1

Renesas RL78/G10 Specifications

General

Brand	Renesas
Model	RL78/G10
Category	Motherboard
Language	English