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RL78/G10 CHAPTER 13 SERIAL INTERFACE IICA

R01UH0384EJ0311 Rev. 3.11 442

Dec 22, 2016

Figure 13-22. Flow When Setting WUP0 = 0 upon Address Match (Including Extension Code Reception)

Waits for five cycles of f

CLK

Executes processing corresponding to the operation to be executed

after checking the operation state of serial interface IICA.

STOP mode state

Yes

WUP0 = 0

Wait

Reading IICS0

INTIICA0 = 1?

Use the following flows to perform the processing to release the STOP mode other than by an interrupt request

(INTIICA0) generated from serial interface IICA.

• Master device operation: Flow shown in Figure 13-23

• Slave device operation:

Cases where the trigger for recovery from the STOP mode is the INTIICA0 interrupt:

Same as the flow in Figure 13-22

Cases where the trigger for recovery from the STOP mode is other than the INTIICA0 interrupt:

Continues the operation with WUP0 = 1 until the INTIICA0 interrupt is generated.

Default Chapter6
- Table of Contents6
Chapter 1 Outline18
- Features18
- List of Part Numbers20
- Pin Configuration (Top View)21
  - 10-Pin Products21
- Pin Identification22
- Block Diagram23
  - 10-Pin Products23
  - 16-Pin Products24
- Outline of Functions25
Chapter 2 Pin Functions27
- Port Functions27
  - 10-Pin Products27
  - 16-Pin Products28
- Functions Other than Port Pins29
  - Functions for each Product29
  - Description of Functions30
- Connection of Unused Pins31
- Block Diagrams of Pins32
Chapter 3 Cpu Architecture40
- Memory Space41
- Processor Registers49
- Instruction Address Addressing59
- Addressing for Processing Data Addresses61
Chapter 4 Port Functions75
- Port Functions75
- Port Configuration75
- Registers Controlling Port Function77
- Port Function Operations84
- Register Settings When an Alternate Function Is Used85
- Cautions When Using Port Function90
  - Cautions on 1-Bit Manipulation Instruction for Port Register N (Pn)90
  - Notes on Specifying the Pin Settings91
Chapter 5 Clock Generator92
- Functions of Clock Generator92
- Configuration of Clock Generator93
- Registers Controlling Clock Generator95
- System Clock Oscillator105
- Clock Generator Operation108
- Controlling Clock110
- Resonator and Oscillator Constants117
Chapter 6 Timer Array Unit119
- Functions of Timer Array Unit121
- Configuration of Timer Array Unit126
  - Timer Counter Register 0N (Tcr0N)130
  - Timer Data Register 0N (Tdr0N)132
- Registers Controlling Timer Array Unit134
- Basic Rules of Timer Array Unit153
  - Basic Rules of Simultaneous Channel Operation Function153
  - Basic Rules of 8-Bit Timer Operation Function (Only Channels 1 and 3)155
- Operation of Counter156
- Channel Output (To0N Pin) Control164
- Timer Input (Ti0N) Control172
- Independent Channel Operation Function of Timer Array Unit174
- Simultaneous Channel Operation Function of Timer Array Unit205
- Cautions When Using Timer Array Unit240
  - Cautions When Using Timer Output240
Chapter 7 12-Bit Interval Timer241
- Functions of 12-Bit Interval Timer241
- Configuration of 12-Bit Interval Timer241
- Registers Controlling 12-Bit Interval Timer242
- 12-Bit Interval Timer Operation245
  - 12-Bit Interval Timer Operation Timing245
  - Start of Count Operation and Re-Enter to HALT/STOP Mode after Returned from HALT/STOP Mode246
Chapter 8 Clock Output/Buzzer Output Controller247
- Functions of Clock Output/Buzzer Output Controller247
- Configuration of Clock Output/Buzzer Output Controller248
- Registers Controlling Clock Output/Buzzer Output Controller248
  - Clock Output Select Register 0 (CKS0)249
  - Registers Controlling Port Functions of Clock Output/Buzzer Output Pin250
- Operations of Clock Output/Buzzer Output Controller251
  - Operation as Output Pin251
Chapter 9 Watchdog Timer252
- Functions of Watchdog Timer252
- Configuration of Watchdog Timer253
- Register Controlling Watchdog Timer254
  - Watchdog Timer Enable Register (WDTE)254
- Operation of Watchdog Timer255
  - Controlling Operation of Watchdog Timer255
  - Setting Time of Watchdog Timer256
Chapter 10 A/D Converter257
- Function of A/D Converter257
- Configuration of A/D Converter259
- Registers Used in A/D Converter260
- A/D Converter Conversion Operations270
- Input Voltage and Conversion Results272
- A/D Converter Operation Modes273
- A/D Converter Setup Flowchart274
  - Setting up A/D Conversion of Voltages on ANI0 to ANI6274
  - Setting up A/D Conversion of the Internal Reference Voltage (16-Pin Products Only)275
- How to Read A/D Converter Characteristics Table276
- Cautions for A/D Converter279
Chapter 11 Comparator282
- Comparator Functions282
- Comparator Configuration282
- Registers Controlling the Comparator284
- Comparator Operation288
- Comparator Setting Flowchart289
  - Enabling Comparator Operation290
  - Disabling Comparator Operation291
Chapter 12 Serial Array Unit292
- Functions of Serial Array Unit293
- Configuration of Serial Array Unit296
  - Shift Register298
  - Serial Data Register 0Nl (Sdr0Nl)298
- Registers Controlling Serial Array Unit299
- Operation Stop Mode320
  - Stopping the Operation by Units320
  - Stopping the Operation by Channels321
- Operation of 3-Wire Serial I/O (CSI00, CSI01) Communication322
- Operation of UART (UART0) Communication382
- Operation of Simplified I C (IIC00) Communication405
Chapter 13 Serial Interface Iica425
- Functions of Serial Interface IICA425
- Configuration of Serial Interface IICA428
- Registers Controlling Serial Interface IICA431
- Timing Charts497
Chapter 14 Interrupt Functions512
- Interrupt Function Types512
- Interrupt Sources and Configuration512
- Registers Controlling Interrupt Functions517
- Interrupt Servicing Operations526
Chapter 15 Key Interrupt Function533
- Functions of Key Interrupt533
- Configuration of Key Interrupt533
- Register Controlling Key Interrupt535
- Key Interrupt Operation538
  - When Not Using the Key Interrupt Flag (KRMD = 0)538
  - When Using the Key Interrupt Flag (KRMD = 1)539
Chapter 16 Standby Function541
- Registers Controlling Standby Function542
  - STOP Mode546
Chapter 17 Reset Function550
- Timing of Reset Operation552
- States of Operation During Reset Periods554
- Register for Confirming Reset Source556
Chapter 18 Selectable Power-On-Reset Circuit558
- Operation of Selectable Power-On-Reset Circuit559
  - Cautions for Selectable Power-On-Reset Circuit560
Chapter 19 Option Byte561
- Format of User Option Byte562
- Format of On-Chip Debug Option Byte564
- Setting of Option Byte565
Chapter 20 Flash Memory566
- Serial Programming by Using Flash Memory Programmer567
  - Programming Environment568
- Writing to Flash Memory by Using External Device (that Incorporates UART)569
- Connection of Pins on Board570
  - Port Pins571
- Serial Programming Method572
  - Flash Memory Programming Mode573
  - Communication Mode574
Chapter 21 On-Chip Debug Function575
- On-Chip Debug Security ID576
- Securing of User Resources577
Chapter 22 Bcd Correction Circuit578
- BCD Correction Circuit Operation579
Chapter 23 Instruction Set581
- Conventions Used in Operation List582
  - Description of Operation Column583
  - Description of Flag Operation Column584
- Operation List585
Chapter 24 Electrical Specifications602
- Absolute Maximum Ratings603
- Oscillator Characteristics604
- DC Characteristics605
  - Supply Current Characteristics607
- AC Characteristics610
- Serial Interface Characteristics613
  - Serial Interface IICA617
- Analog Characteristics618
  - Comparator Characteristics619
  - SPOR Circuit Characteristics620
- Flash Memory Programming Characteristics621
- Timing of Entry to Flash Memory Programming Modes622
Chapter 25 Package Drawings623
- Index624
Appendix A Revision History625
A.2 Revision History of Preceding Editions626

Brand	Renesas
Model	RL78/G10
Category	Motherboard
Language	English

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