EasyManua.ls Logo

Renesas RL78/G10 - Page 469

Renesas RL78/G10
637 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Loading...
RL78/G10 CHAPTER 13 SERIAL INTERFACE IICA
R01UH0384EJ0311 Rev. 3.11 452
Dec 22, 2016
(2) Master operation in multi-master system
Figure 13-28. Master Operation in Multi-Master System (1/3)
IICWL0, IICWH0 XXH
IICF0 0XH
Setting STCEN0 and IICRSV0
Setting po
Setting PER0 register
rt
SPT0 = 1
SVA0 XXH
SPIE0 = 1
STAR
T
Slave operation
Slave operation
Releases the bus for a specific period.
Bus status is
being checked.
Ye s
Checking bus status
Note
Master operation
starts?
Enables reserving
communication.
Disables reserving
communication.
SPD0 = 1?
STCEN0 = 1?
IICRSV0 = 0?
A
Selects a transfer clock.
Sets a local addres
Release the serial interface IICA0 from the reset status and start clock supply.
s.
Sets a start condition.
(Communication start request)
(No communication start request)
Waiting to be specified as a slave by other master
Waiting for a communication start request (depends on user program)
Prepares for starting
communication
(generates a stop condition
).
Waits for detection
of the stop condition.
No
Ye s
Y
es
No
INTIICA0
interrupt occurs?
INTIICA0
interr
upt occurs?
Y
es
No
Ye s
No
SPD0 = 1?
Ye s
No
Slave operation
No
INTIICA0
interr
upt occurs?
Ye s
No
1
B
SPIE0 = 0
Ye s
No
Waits for a communication request
.
Waits for a communication Initial setting
IICCTL00 1XX111XXB
IICE0 = 1
IICCTL00 0XX111XXB
ACKE0 = WTIM0 = SPIE0 = 1
Setting of the port used alternatively as the pin to be used.
First, set the po
(see 13.3.8 Registers controlling port functions of IICA serial input/output pins).
(see 13.3.8 Registers controlling port functions of IICA serial input/output pins).
rt to input mode and the output latch to 0
Setting port
Set the port from input mode to output mode and enable the output of the I
2
C bus
Setting IICCTL01
Note Confirm that the bus is released (CLD0 bit = 1, DAD0 bit = 1) for a specific period (for example, for a period of
one frame). If the SDAA0 pin is constantly at low level, decide whether to release the I
2
C bus (SCLA0 and
SDAA0 pins = high level) in conformance with the specifications of the product that is communicating.

Table of Contents

Related product manuals