RL78/G10 CHAPTER 16 STANDBY FUNCTION
R01UH0384EJ0311 Rev. 3.11 528
Dec 22, 2016
(b) HALT mode release by reset signal generation
When the reset signal is generated, HALT mode is released, and then, as in the case with a normal reset
operation, the program is executed after branching to the reset vector address.
Figure 16-2. HALT Mode Release by Reset Signal Generation
(1) When high-speed on-chip oscillator clock is used as CPU clock
HALT
instruction
Reset signal
High-speed on-chip
oscillator clock
Normal operation
(
High-speed on-chip
oscillator clock)
Normal operation
(High-speed on-chip oscillator clock)
HALT mode
Reset
period
Oscillates
Oscillation
stopped
Oscillates
Status of CPU
Wait for oscillation
accuracy stabilization
Reset processing
(2) When high-speed system clock is used as CPU clock (16-pin products only)
HALT
instruction
Reset signal
High-speed
system clock
(X1 oscillation)
HALT mode
Reset
period
Oscillates
Oscillation
stopped
Oscillates
Status of CPU
Normal operation
(high-speed
system clock)
Oscillation stabilization time
(check by using OSTC register)
Normal operation
(High-speed on-chip oscillator clock)
Oscillation
stopped
Reset processing
Note For the reset processing time, see CHAPTER 17 RESET FUNCTION.
For the reset processing time of the SPOR circuit, see CHAPTER 18 SELECTABLE POWER-ON-RESET
CIRCUIT.
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