Sel 2414 - Message Reception Overview; Message Decoding and Integrity Checks

G.2
SEL-2414 Transformer Monitor Instruction Manual Date Code 20130214
MIRRORED BITS Communications
Overview
Transmitting at longer intervals for baud rates above 9600 avoids overflowing
devices that receive M
IRRORED BITS at a slower rate.
Message Reception Overview
During synchronized MIRRORED BITS communications with the communications
channel in normal state, the device decodes and checks each received message. If
the message is valid, the device sends each received logic bit (RMBn, where n =
1 through 8) to the corresponding pickup and dropout security counters, that in
turn set or clear the RMBnA and RMBnB device element bits.
Message Decoding and Integrity Checks
Set the RX_ID of the local SEL-2414 to match the TX_ID of the remote
SEL-2414. The SEL-2414 provides indication of the status of each M
IRRORED
B
ITS communications channel with Device Word bits ROKA (receive OK) and
ROKB. During normal operation, the device sets the ROKc (c = A or B). Upon
detecting any of the following conditions, the device clears the ROKc bit:
➤ The device is disabled.
➤ MIRRORED BITS are not enabled.
➤ Parity, framing, or overrun errors.
➤ Receive message identification error.
➤ No message received in the time three messages have been sent
when PROTO = MBc, or seven messages have been sent when
PROTO = MB8c.
➤ Loopback is enabled.
The device asserts ROKc only after successful synchronization as described
below and two consecutive messages pass all of the data checks described above.
After ROKc is reasserted, received data may be delayed while passing through
the security counters described below.
While ROKc is deasserted, the device does not transfer new RMB data to the
pickup-dropout security counters described below. Instead, the device sends one
of the user-definable default values to the security counter inputs. For each
RMBn, use the RXDFLT setting to determine the default state the M
IRRORED
B
ITS should use in place of received data if an error condition is detected. The
setting is a mask of 1s, 0s, and/or Xs (for RMB1A–RMB8A), where X represents
the most recently received valid value. The positions of the 1s and 0s correspond
to the respective positions of the M
IRRORED BITS in the Device Word bits (see
Appendix H: Device Word Bits). Table G.2 is an extract of Appendix H: Device
Word Bits, showing the positions of the M
IRRORED BITS.
Tab le G.1 N um ber of M IRRORED BITS Messages for Different Baud
Baud Rate Transmission Rate of MIRRORED BITS Packets
2400 15 ms
4800 7.5 ms
9600 4 times a power system cycle (automatic pacing mode)
19200 4 times a power system cycle (automatic pacing mode)
38400 4 times a power system cycle (automatic pacing mode)