ST STM32G473 User Manual

Reset and clock control (RCC) RM0440
326/2126 RM0440 Rev 4
7.4.26 Peripherals independent clock configuration register (RCC_CCIPR)
Address: 0x88
Reset value: 0x0000 0000
Access: no wait states, word, half-word and byte access
Bit 15 SPI4SMEN: SPI4 timer clocks enable during Sleep and Stop modes
Set and cleared by software.
0: SPI4 clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: SPI4 clocks enabled by the clock gating
(1)
during Sleep and Stop mode
Bit 14 USART1SMEN: USART1clocks enable during Sleep and Stop modes
Set and cleared by software.
0: USART1clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: USART1clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bit 13 TIM8SMEN: TIM8 timer clocks enable during Sleep and Stop modes
Set and cleared by software.
0: TIM8 timer clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: TIM8 timer clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bit 12 SPI1SMEN: SPI1 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: SPI1 clocks disabled by the clock gating during
(1)
Sleep and Stop modes
1: SPI1 clocks enabled by the clock gating during
(1)
Sleep and Stop modes
Bit 11 TIM1SMEN: TIM1 timer clocks enable during Sleep and Stop modes
Set and cleared by software.
0: TIM1 timer clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: TIM1P timer clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bits 10:1 Reserved, must be kept at reset value.
Bit 0 SYSCFGSMEN: SYSCFG + COMP + VREFBUF + OPAMP clocks enable during Sleep and
Stop modes
Set and cleared by software.
0: SYSCFG + COMP + VREFBUF + OPAMP clocks disabled by the clock gating
(1)
during
Sleep and Stop modes
1: SYSCFG + COMP + VREFBUF + OPAMP clocks enabled by the clock gating
(1)
during
Sleep and Stop modes
1. This register only configures the clock gating, not the clock source itself. Most of the peripherals are clocked by a single
clock (AHB or APB clock), which is always disabled in Stop mode. In this case setting the bit has no effect in Stop mode.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADC345SEL[1:0] ADC12SEL[1:0] CLK48SEL[1:0] FDCANSEL[1:0] I2S23SEL[1:0] SAI1SEL[1:0] LPTIM1SEL[1:0 I2C3SEL[1:0]
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15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2C2SEL[1:0] I2C1SEL[1:0]
LPUART1SEL
[1:0]
UART5SEL
[1:0]
UART4SEL
[1:0]
USART3SEL
[1:0]
USART2SEL
[1:0]
USART1SEL
[1:0]
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ST STM32G473 Specifications

General

Brand	ST
Model	STM32G473
Category	Microcontrollers
Language	English