RL78/G10 CHAPTER 6 TIMER ARRAY UNIT
R01UH0384EJ0311 Rev. 3.11 169
Dec 22, 2016
Figure 6-49. Example of Basic Timing of Operation as Frequency Divider (MD00n = 1)
TS0n
TE0n
TI0n
TDR0n
TCR0n
TO0n
INTTM0n
0002H
Divided
by 6
0001H
0
0000H
1
2
0
1
2
0
1
0
1
0
1
0
1
0
1
2
Divided
by 4
Remark n: Channel number
n = 0 (for 10-pin products); n = 0, 3 (for 16-pin products)
TS0n: Bit n of timer channel start register 0 (TS0)
TE0n: Bit n of timer channel enable status register 0 (TE0)
TI0n: TI0n pin input signal
TCR0n: Timer count register 0n (TCR0n)
TDR0n: Timer data register 0n (TDR0n)
TO0n: TO0n pin output signal
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