Renesas RL78/G10

RL78/G10 CHAPTER 6 TIMER ARRAY UNIT
R01UH0384EJ0311 Rev. 3.11 189
Dec 22, 2016
Figure 6-64. Block Diagram of Operation for One-Shot Pulse Output
Interrupt signal
(INTTM0n)
Interrupt
controller
Clock selection
Trigger selection
Operation clock
CK00
CK01
TS0n
Interrupt signal
(INTTM0p)
Interrupt
controller
Clock selection
Trigger selection
Operation clock
CK00
CK01
TO0p pin
Output
controller
Master channel
(one-count mode)
Slave channel
(one-count mode)
Edge
detection
TI0n pin
Timer counter
register 0n (TCR0n)
Timer data
register 0n (TDR0n)
Timer counter
register 0p (TCR0p)
Timer data
register 0p (TDR0p)
Noise
filter
TNFEN0n
Remark n: Master channel number (n = 0, 2)
p: Slave channel number (n < p ≤ 3)