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RL78/G10
CHAPTER 6 TIMER
ARRA
Y UNIT
R01UH0384EJ031
1 Rev
. 3.1
1
189
Dec 22, 2016
Figure 6-64. Block Diagram of Op
eration for One-Shot Pulse Outp
ut
Interrupt signal
(INTTM0n)
Interrupt
controller
Clock selection
Trigger selection
Operation clock
CK00
CK01
TS0n
Interrupt signal
(INTTM0p)
Interrupt
controller
Clock selection
Trigger selection
Operation clock
CK00
CK01
TO0p pin
Output
controller
Master channel
(one-count mode)
Slave channel
(one-count mode)
Edge
detection
TI0n pin
Timer counter
register 0n (TCR0n)
Timer data
register 0n (TDR0n)
Timer counter
register 0p (TCR0p)
Timer data
register 0p (TDR0p)
Noise
filter
TNFEN0n
Remark
n: Master channel n
umber (n = 0, 2)
p: Slave channel num
ber (n < p
≤
3)
205
207
Table of Contents
Default Chapter
6
Table of Contents
6
Chapter 1 Outline
18
Features
18
List of Part Numbers
20
Pin Configuration (Top View)
21
10-Pin Products
21
Pin Identification
22
Block Diagram
23
10-Pin Products
23
16-Pin Products
24
Outline of Functions
25
Chapter 2 Pin Functions
27
Port Functions
27
10-Pin Products
27
16-Pin Products
28
Functions Other than Port Pins
29
Functions for each Product
29
Description of Functions
30
Connection of Unused Pins
31
Block Diagrams of Pins
32
Chapter 3 Cpu Architecture
40
Memory Space
41
Internal Program Memory Space
44
Mirror Area
46
Internal Data Memory Space
47
Special Function Register (SFR) Area
47
Extended Special Function Register (2Nd SFR: 2Nd Special Function Register) Area
47
Data Memory Addressing
48
Processor Registers
49
Control Registers
49
General-Purpose Registers
51
ES and CS Registers
52
Special Function Registers (Sfrs)
53
Extended Special Function Registers (2Nd Sfrs: 2Nd Special Function Registers)
56
Instruction Address Addressing
59
Relative Addressing
59
Immediate Addressing
59
Register Direct Addressing
60
Table Indirect Addressing
60
Addressing for Processing Data Addresses
61
Implied Addressing
61
Register Addressing
61
Direct Addressing
62
Short Direct Addressing
63
SFR Addressing
64
Register Indirect Addressing
65
Based Addressing
66
Based Indexed Addressing
70
Stack Addressing
71
Chapter 4 Port Functions
75
Port Functions
75
Port Configuration
75
Port 0
76
Port 4
76
Port 12
76
Port 13
76
Registers Controlling Port Function
77
Port Mode Registers 0, 4 (PM0, PM4)
78
Port Registers 0, 4, 12, 13 (P0, P4, P12, P13)
79
Pull-Up Resistor Option Registers 0, 4, 12 (PU0, PU4, PU12)
80
Port Output Mode Register 0 (POM0)
81
Port Mode Control Register 0 (PMC0)
82
Peripheral I/O Redirection Register (PIOR)
83
Port Function Operations
84
Writing to I/O Port
84
Reading from I/O Port
84
Operations on I/O Port
84
Register Settings When an Alternate Function Is Used
85
Basic Concepts on Using an Alternate Function
85
Register Settings for Alternate Functions that Do Not Use an Output Function
86
Example of Register Settings for Port and Alternate Functions Used
86
Cautions When Using Port Function
90
Cautions on 1-Bit Manipulation Instruction for Port Register N (Pn)
90
Notes on Specifying the Pin Settings
91
Chapter 5 Clock Generator
92
Functions of Clock Generator
92
Configuration of Clock Generator
93
Registers Controlling Clock Generator
95
Clock Operation Mode Control Register (CMC)
96
System Clock Control Register (CKC)
97
Clock Operation Status Control Register (CSC)
98
Oscillation Stabilization Time Counter Status Register (OSTC)
99
Oscillation Stabilization Time Select Register (OSTS)
101
Peripheral Enable Register 0 (PER0)
102
Operation Speed Mode Control Register (OSMC)
103
High-Speed On-Chip Oscillator Frequency Selection Register (HOCODIV)
104
System Clock Oscillator
105
X1 Oscillator (16-Pin Products Only)
105
High-Speed On-Chip Oscillator
108
Low-Speed On-Chip Oscillator
108
Clock Generator Operation
108
Controlling Clock
110
Example of Setting High-Speed On-Chip Oscillator
110
Example of Setting X1 Oscillation Clock
111
CPU Clock Status Transition Diagram
112
Condition before Changing CPU Clock and Processing after Changing CPU Clock
115
Time Required for Switchover of CPU Clock and Main System Clock
116
Conditions before Clock Oscillation Is Stopped
116
Resonator and Oscillator Constants
117
Chapter 6 Timer Array Unit
119
Functions of Timer Array Unit
121
Independent Channel Operation Function
121
Simultaneous Channel Operation Function
123
8-Bit Timer Operation Function (Channels 1 and 3 Only)
125
Configuration of Timer Array Unit
126
Timer Counter Register 0N (Tcr0N)
130
Timer Data Register 0N (Tdr0N)
132
Registers Controlling Timer Array Unit
134
Peripheral Enable Register 0 (PER0)
135
Timer Clock Select Register 0 (TPS0)
136
Timer Mode Register 0N (Tmr0N)
137
Timer Status Register 0N (Tsr0N)
142
Timer Channel Enable Status Register 0 (TE0, TEH0 (8-Bit Mode))
143
Timer Channel Start Register 0 (TS0, TSH0 (8-Bit Mode))
144
Timer Channel Stop Register 0 (TT0, TTH0 (8-Bit Mode))
145
Timer Output Enable Register 0 (TOE0)
146
Timer Output Register 0 (TO0)
147
Timer Output Level Register 0 (TOL0)
148
Timer Output Mode Register 0 (TOM0)
149
Noise Filter Enable Register 1 (NFEN1)
150
Input Switch Control Register (ISC)
151
Registers Controlling Port Functions of Pins to be Used for Timer I/O
152
Basic Rules of Timer Array Unit
153
Basic Rules of Simultaneous Channel Operation Function
153
Basic Rules of 8-Bit Timer Operation Function (Only Channels 1 and 3)
155
Operation of Counter
156
Count Clock (F )
156
Start Timing of Counter
158
Counter Operation
159
Channel Output (To0N Pin) Control
164
To0N Pin Output Circuit Configuration
164
To0N Pin Output Setting
165
Cautions on Channel Output Operation
166
Collective Manipulation of To0N Bit
170
Timer Interrupt and To0N Pin Output at Count Operation Start
171
Timer Input (Ti0N) Control
172
Ti0N Input Circuit Configuration
172
Noise Filter
172
Cautions on Channel Input Operation
173
Independent Channel Operation Function of Timer Array Unit
174
Operation as Interval Timer/Square Wave Output
174
Operation as External Event Counter
180
Operation as Frequency Divider (Only Channels 0 and 3)
185
Operation as Input Pulse Interval Measurement
190
Operation as Input Signal High-/Low-Level Width Measurement
195
Operation as Delay Counter
200
Simultaneous Channel Operation Function of Timer Array Unit
205
Operation as One-Shot Pulse Output
205
Two-Channel Input with One-Shot Pulse Output Function
214
Operation as PWM Output Function
223
Operation as Multiple PWM Output Function
231
Cautions When Using Timer Array Unit
240
Cautions When Using Timer Output
240
Chapter 7 12-Bit Interval Timer
241
Functions of 12-Bit Interval Timer
241
Configuration of 12-Bit Interval Timer
241
Registers Controlling 12-Bit Interval Timer
242
Peripheral Enable Register 0 (PER0)
242
Operation Speed Mode Control Register (OSMC)
243
Interval Timer Control Register (ITMCH, ITMCL)
244
12-Bit Interval Timer Operation
245
12-Bit Interval Timer Operation Timing
245
Start of Count Operation and Re-Enter to HALT/STOP Mode after Returned from HALT/STOP Mode
246
Chapter 8 Clock Output/Buzzer Output Controller
247
Functions of Clock Output/Buzzer Output Controller
247
Configuration of Clock Output/Buzzer Output Controller
248
Registers Controlling Clock Output/Buzzer Output Controller
248
Clock Output Select Register 0 (CKS0)
249
Registers Controlling Port Functions of Clock Output/Buzzer Output Pin
250
Operations of Clock Output/Buzzer Output Controller
251
Operation as Output Pin
251
Chapter 9 Watchdog Timer
252
Functions of Watchdog Timer
252
Configuration of Watchdog Timer
253
Register Controlling Watchdog Timer
254
Watchdog Timer Enable Register (WDTE)
254
Operation of Watchdog Timer
255
Controlling Operation of Watchdog Timer
255
Setting Time of Watchdog Timer
256
Chapter 10 A/D Converter
257
Function of A/D Converter
257
Configuration of A/D Converter
259
Registers Used in A/D Converter
260
Peripheral Enable Register 0 (PER0)
261
A/D Converter Mode Register 0 (ADM0)
262
A/D Converter Mode Register 2 (ADM2)
266
A/D Conversion Result Higher-Order Bit Storage Register (ADCRH)
266
A/D Conversion Result Lower-Order Bit Storage Register (ADCRL)
267
Analog Input Channel Specification Register (ADS)
268
A/D Test Register (ADTES)
269
Registers Controlling Port Function of Analog Input Pins
269
A/D Converter Conversion Operations
270
Input Voltage and Conversion Results
272
A/D Converter Operation Modes
273
A/D Converter Setup Flowchart
274
Setting up A/D Conversion of Voltages on ANI0 to ANI6
274
Setting up A/D Conversion of the Internal Reference Voltage (16-Pin Products Only)
275
How to Read A/D Converter Characteristics Table
276
Resolution
276
Overall Error
276
Quantization Error
276
Zero-Scale Error
277
Full-Scale Error
277
Integral Linearity Error
277
Differential Linearity Error
277
Conversion Time
278
Sampling Time
278
Cautions for A/D Converter
279
Operating Current in STOP Mode
279
Input Range of ANI0 to ANI6 Pins
279
Conflicting Operations
279
Noise Countermeasures
279
Analog Input (Anin) Pins
280
Input Impedance of Analog Input (Anin) Pins
280
Interrupt Request Flag (ADIF)
281
Conversion Results Just after A/D Conversion Start
281
A/D Conversion Result Register (ADCRH, ADCRL) Read Operation
281
Internal Equivalent Circuit
281
Starting the A/D Converter
281
Chapter 11 Comparator
282
Comparator Functions
282
Comparator Configuration
282
Registers Controlling the Comparator
284
Peripheral Enable Register 0 (PER0)
284
Comparator Mode Setting Register (COMPMDR)
285
Comparator Filter Control Register (COMPFIR)
286
Comparator Output Control Register (COMPOCR)
287
Registers Controlling Port Functions of Comparator I/O Pins
287
Comparator Operation
288
Comparator 0 Digital Filter Operation
289
Comparator 0 Interrupt Operation
289
Comparator 0 Output
289
Comparator Setting Flowchart
289
Enabling Comparator Operation
290
Disabling Comparator Operation
291
Chapter 12 Serial Array Unit
292
Functions of Serial Array Unit
293
3-Wire Serial I/O (CSI00, CSI01)
293
Uart (Uart0)
294
Iic00)
295
Configuration of Serial Array Unit
296
Shift Register
298
Serial Data Register 0Nl (Sdr0Nl)
298
Registers Controlling Serial Array Unit
299
Peripheral Enable Register 0 (PER0)
300
Serial Clock Select Register 0 (SPS0)
301
Serial Mode Register 0N (Smr0Nh, Smr0Nl)
302
Serial Communication Operation Setting Register 0N (Scr0Nh, Scr0Nl)
304
Serial Data Register 0N (Sdr0Nh, Sdr0Nl)
306
Serial Flag Clear Trigger Register 0N (Sir0N)
307
Serial Status Register 0N (Ssr0N)
308
Serial Channel Start Register 0 (SS0)
310
Serial Channel Stop Register 0 (ST0)
311
Serial Channel Enable Status Register 0 (SE0)
312
Serial Output Enable Register 0 (SOE0)
313
Serial Output Register 0 (SO0)
314
Serial Clock Output Register 0 (CKO0)
315
Serial Output Level Register 0 (SOL0)
316
Noise Filter Enable Register 0 (NFEN0)
317
Input Switch Control Register (ISC)
318
Registers Controlling Port Functions of Serial Input/Output Pins
319
Operation Stop Mode
320
Stopping the Operation by Units
320
Stopping the Operation by Channels
321
Operation of 3-Wire Serial I/O (CSI00, CSI01) Communication
322
Master Transmission
323
Master Reception
333
Master Transmission/Reception
342
Slave Transmission
352
Slave Reception
362
Slave Transmission/Reception
369
Calculating Transfer Clock Frequency
379
Procedure for Processing Errors that Occurred During 3-Wire Serial I/O (CSI00, CSI01)
381
Communication
381
Operation of UART (UART0) Communication
382
UART Transmission
383
UART Reception
393
Calculating Baud Rate
400
Procedure for Processing Errors that Occurred During UART (UART0) Communication
404
Operation of Simplified I C (IIC00) Communication
405
Address Field Transmission
406
Data Transmission
412
Data Reception
416
Stop Condition Generation
421
Calculating Transfer Rate
422
Procedure for Processing Errors that Occurred During Simplified I C (IIC00) Communication
424
Chapter 13 Serial Interface Iica
425
Functions of Serial Interface IICA
425
Configuration of Serial Interface IICA
428
Registers Controlling Serial Interface IICA
431
Peripheral Enable Register 0 (PER0)
432
IICA Control Register 00 (IICCTL00)
432
IICA Status Register 0 (IICS0)
437
IICA Flag Register 0 (IICF0)
439
IICA Control Register 01 (IICCTL01)
441
IICA Low-Level Width Setting Register 0 (IICWL0)
443
IICA High-Level Width Setting Register 0 (IICWH0)
443
Registers Controlling Port Functions of IICA Serial Input/Output Pins
444
I 2 C Bus Mode Functions
445
Pin Configuration
445
Setting Transfer Clock by Using IICWL0 and IICWH0 Registers
446
I 2 C Bus Definitions and Control Methods
447
Start Conditions
447
Addresses
448
Transfer Direction Specification
448
Acknowledge (ACK)
449
Stop Condition
450
Wait
451
Canceling Wait
453
Interrupt Request (INTIICA0) Generation Timing and Wait Control
454
Address Match Detection Method
455
Error Detection
455
Extension Code
455
Arbitration
456
Wakeup Function
458
Communication Reservation
461
Cautions
465
Communication Operations
466
Timing of I 2 C Interrupt Request (INTIICA0) Occurrence
476
Timing Charts
497
Chapter 14 Interrupt Functions
512
Interrupt Function Types
512
Interrupt Sources and Configuration
512
Registers Controlling Interrupt Functions
517
External Interrupt Rising Edge Enable Register 0 (EGP0)
517
Interrupt Request Flag Registers (IF0L, IF0H, IF1L)
519
Interrupt Mask Flag Registers (MK0L, MK0H, MK1L)
521
Priority Specification Flag Registers (PR00L, PR00H, PR10L, PR10H, PR01L, PR11L)
522
External Interrupt Falling Edge Enable Register 0 (EGN0)
524
Program Status Word (PSW)
525
Interrupt Servicing Operations
526
Maskable Interrupt Request Acknowledgment
526
Software Interrupt Request Acknowledgment
528
Multiple Interrupt Servicing
528
Interrupt Request Hold
532
Chapter 15 Key Interrupt Function
533
Functions of Key Interrupt
533
Configuration of Key Interrupt
533
Register Controlling Key Interrupt
535
Key Interrupt Control Register (KRCTL)
535
Key Return Mode Register (KRM0)
536
Key Return Flag Register (KRF)
537
Registers Controlling Port Functions of Key Interrupt Input Pins
537
Key Interrupt Operation
538
When Not Using the Key Interrupt Flag (KRMD = 0)
538
When Using the Key Interrupt Flag (KRMD = 1)
539
Chapter 16 Standby Function
541
Registers Controlling Standby Function
542
STOP Mode
546
Chapter 17 Reset Function
550
Timing of Reset Operation
552
States of Operation During Reset Periods
554
Register for Confirming Reset Source
556
Chapter 18 Selectable Power-On-Reset Circuit
558
Operation of Selectable Power-On-Reset Circuit
559
Cautions for Selectable Power-On-Reset Circuit
560
Chapter 19 Option Byte
561
Format of User Option Byte
562
Format of On-Chip Debug Option Byte
564
Setting of Option Byte
565
Chapter 20 Flash Memory
566
Serial Programming by Using Flash Memory Programmer
567
Programming Environment
568
Writing to Flash Memory by Using External Device (that Incorporates UART)
569
Connection of Pins on Board
570
Port Pins
571
Serial Programming Method
572
Flash Memory Programming Mode
573
Communication Mode
574
Chapter 21 On-Chip Debug Function
575
On-Chip Debug Security ID
576
Securing of User Resources
577
Chapter 22 Bcd Correction Circuit
578
BCD Correction Circuit Operation
579
Chapter 23 Instruction Set
581
Conventions Used in Operation List
582
Description of Operation Column
583
Description of Flag Operation Column
584
Operation List
585
Chapter 24 Electrical Specifications
602
Absolute Maximum Ratings
603
Oscillator Characteristics
604
DC Characteristics
605
Supply Current Characteristics
607
AC Characteristics
610
Serial Interface Characteristics
613
Serial Interface IICA
617
Analog Characteristics
618
Comparator Characteristics
619
SPOR Circuit Characteristics
620
Flash Memory Programming Characteristics
621
Timing of Entry to Flash Memory Programming Modes
622
Chapter 25 Package Drawings
623
Index
624
Appendix A Revision History
625
A.2 Revision History of Preceding Editions
626
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Renesas RL78/G10 Specifications
General
Brand
Renesas
Model
RL78/G10
Category
Motherboard
Language
English
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