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Renesas RL78/G10 - Page 271

Renesas RL78/G10
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RL78/G10 CHAPTER 10 A/D CONVERTER
R01UH0384EJ0311 Rev. 3.11 254
Dec 22, 2016
Figure 10-12. Conversion Operation of A/D Converter
1 is written to ADCS
ADCS
Sampling
time
A/D converter
operation
Conversion
standby
Sampling
A/D conversion
Conversion
standby
Conversion
result
Conversion
result
Undefined
SAR
A
DCRH, ADCRL
INT
AD
Conversion time
A/D conversion is performed once when the bit 7 (ADCS) of the A/D converter mode register 0 (ADM0) is set to 1 by
software. The ADCS bit is automatically cleared to 0 after A/D conversion ends.
Reset signal generation clears the A/D conversion result register (ADCRH, ADCRL) to 00H.

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