RL78/G10 CHAPTER 12 SERIAL ARRAY UNIT
R01UH0384EJ0311 Rev. 3.11 286
Dec 22, 2016
Figure 12-5. Format of Serial Mode Register 0n (SMR0nH, SMR0nL) (2/2)
Address: F0111H (SMR00H), F0113H (SMR01H) Address: F0110H (SMR00L), F0112H (SMR01L)
After reset: 00H R/W After reset: 20H R/W
Symbol: SMR0nH Symbol: SMR0nL
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
CKS
0n
CCS
0n
0 0 0 0 0 STS
0n
Note 1
0 SIS
0n0
Note 2
1 0 0 MD
0n2
MD
0n1
MD
0n0
SIS0n0
Note 2
Controls inversion of level of receive data of UART0
0
Falling edge is detected as the start bit.
The input communication data is captured as is.
1
Rising edge is detected as the start bit.
The input communication data is inverted and captured.
MD0n2 MD0n1 Setting of operation mode of channel n
0 0 CSI mode
0 1 UART mode
1 0 Simplified I
2
C mode
1 1 Setting prohibited
MD0n0 Selection of interrupt source of channel n
0 Transfer end interrupt
1 Buffer empty interrupt
(Occurs when data is transferred from the SDR0nL register to the shift register.)
For successive transmission, the next transmit data is written by setting the MD0n0 bit to 1 when SDR0nL data
has run out.
Notes 1. Provided in the SMR01H register only.
2. Provided in the SMR01L register only.
Caution Do not change the initial values of the following bits.
SMR00H: Be sure to clear bits 0 to 5 to 0.
SMR01H: Be sure to clear bits 1 to 5 to 0.
SMR00L: Be sure to clear bits 3, 4, 6, and 7 to 0, and set bit 5 to 1.
SMR01L: Be sure to clear bits 3, 4, and 7 to 0, and set bit 5 to 1.
Remark n: Channel number (n = 0, 1)
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