RL78/G10 CHAPTER 12 SERIAL ARRAY UNIT
R01UH0384EJ0311 Rev. 3.11 292
Dec 22, 2016
Figure 12-9. Format of Serial Status Register 0n (SSR0n) (2/2)
Address: F0100H (SSR00), F0102H (SSR01) , After reset: 00H R
Symbol
7 6 5 4 3 2 1 0
SSR0n 0 TSF0n BFF0n 0 0 FEF0n
Note
PEF0n OVF0n
FEF0n
Note
Framing error detection flag of channel n
0
No error occurs.
1 An error occurs (during UART reception).
<Clear condition>
• 1 is written to the FECT0n bit of the SIR0n register.
<Set condition>
• A stop bit is not detected when UART reception ends.
PEF0n Parity / ACK error detection flag of channel n
0 No error occurs.
1 Parity error occurs (during UART reception) or ACK is not detected (during I
2
C transmission).
<Clear condition>
• 1 is written to the PECT0n bit of the SIR0n register.
<Set condition>
• The parity of the transmit data and the parity bit do not match when UART reception ends (parity error).
• No ACK signal is returned from the slave channel at the ACK reception timing during I
2
C transmission (ACK is
not detected).
OVF0n Overrun error detection flag of channel n
0 No error occurs.
1 An error occurs
<Clear condition>
• 1 is written to the OVCT0n bit of the SIR0n register.
<Set condition>
• Even though receive data is stored in the SDR0nL register, that data is not read and transmit data or the next
receive data is written while the RXE0n bit of the SCR0nH register is set to 1 (reception or transmission and
reception mode in each communication mode).
• Transmit data is not ready for slave transmission or transmission and reception in CSI mode.
Note Provided in the SSR01 register only.
Remark n: Channel number (n = 0, 1)
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