RL78/G10 CHAPTER 12 SERIAL ARRAY UNIT
R01UH0384EJ0311 Rev. 3.11 323
Dec 22, 2016
(4) Processing flow (in continuous reception mode)
Figure 12-36. Timing Chart of Master Reception (in Continuous Reception Mode) (Type 1: DAP0n = 0, CKP0n = 0)
SS0n
SE0n
SDR0nL
SCKp pin
SIp pin
INTCSIp
TSF0n
Dummy data
Dummy data
Write
Write
Reception & shift operation
BFF0n
<1>
<2>
Dummy data
Write
MD0n0
Receive data 2
Receive data 1
Receive data 1
Data reception
ST0n
Shift
register 0n
Read Read
Read
Receive data 2
Receive data 3
Reception & shift operation
Reception & shift operation
Data reception Data reception
<2>
<2>
<8>
<5>
<3> <3> <4> <4><3> <6> <7>
Receive data 3
Caution The MD0n0 bit can be rewritten even during operation.
However, rewrite it before receive of the last bit is started, so that it has been rewritten before the
transfer end interrupt of the last receive data.
Remarks 1. <1> to <8> in the figure correspond to <1> to <8> in Figure 12-37 Flowchart of Master Reception
(in Continuous Reception Mode).
2. n = 0, 1, p: CSI number (p = 00, 01)
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