RL78/G10 CHAPTER 12 SERIAL ARRAY UNIT
R01UH0384EJ0311 Rev. 3.11 333
Dec 22, 2016
(4) Processing flow (in continuous transmission/reception mode)
Figure 12-44. Timing Chart of Master Transmission/Reception (in Continuous Transmission/Reception Mode)
(Type 1: DAP0n = 0, CKP0n = 0)
SS0n
SE0n
SDR0nL
SCKp pin
SIp pin
INTCSIp
TSF0n
SOp pin
BFF0n
<1>
Note 1
MD0n0
ST0n
Transmit data 1 Transmit data 2
Transmit data 3Receive data 1 Receive data 2
Receive data 3
Receive data 1 Receive data 2 Receive data 3
Transmit data 1
Transmit data 2 Transmit data 3
Reception & shift operation Reception & shift operation
Reception & shift operation
Data transmission/reception Data transmission/reception Data transmission/reception
Write
Write
Write
Read
Read
Read
<8>
<2> <2> <2><3> <2> <2><4> <4>
<5>
<6> <7>
Note 2
Note 2
Shift
register 0n
Notes 1. If transmit data is written to the SDR0nL register while the BFF0n bit of serial status register 0n (SSR0n)
is 1 (valid data is stored in serial data register 0n (SDR0nL)), the transmit data is overwritten.
2. The transmit data can be read by reading the SDR0nL register during this period. At this time, the
transfer operation is not affected.
Caution The MD0n0 bit of serial mode register 0n (SMR0nL) can be rewritten even during operation.
However, rewrite it before transfer of the last bit is started, so that it has been rewritten before
the transfer end interrupt of the last transmit data.
Remarks 1. <1> to <8> in the figure correspond to <1> to <8> in Figure 12-45 Flowchart of Master
Transmission/Reception (in Continuous Transmission/Reception Mode).
2. n = 0, 1, p: CSI number (p = 00, 01)
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