RL78/G10 CHAPTER 12 SERIAL ARRAY UNIT
R01UH0384EJ0311 Rev. 3.11 394
Dec 22, 2016
Figure 12-89. Flowchart of simplified I
2
C Address Field Transmission
For the initial setting, refer to Figure 12-87.
No
Yes
Yes
Communication error
processing
To data transmission flow
and data reception flow
Writing 0 to the SO0n bit
Address field
transmission completed
Transfer end inte
rupt
enerated?
Writing address and R/W data
to SIOr (SDR0nL)
Writing 1 to the SS0n bit
Responded ACK?
Writing 1 to the SOE0n bit
Writing 0 to the CKO0n bit
Default setting
Wait
No
Transmitting address field
Wait for address field transmission complete.
(Clear the interrupt request flag)
Transmitting address field
To serial operation enable status
Enable serial output
Prepare to communicate the SCL signal is
fall
To secure a hold time of SCL signal
Start condition generate
Setting the SO0n bit to 0
Confirm ACK (acknowledgment) from the slave
by checking the setting of the PEF0n bit.
If ACK has been received (PEF0n = 0), proceed
with further processing.
If NACK has been received (PEF0n = 1), error
handling is required.
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