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Renesas RL78/G10 - Page 410

Renesas RL78/G10
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RL78/G10 CHAPTER 12 SERIAL ARRAY UNIT
R01UH0384EJ0311 Rev. 3.11 393
Dec 22, 2016
(3) Processing flow
Figure 12-88. Timing Chart of Address Field Transmission
D7 D6 D5 D4 D3 D2 D1 D0
R/W
D7 D6
SS0n
SE0n
SOE0n
SDR0nL
SCLr output
SDAr output
SDAr input
Shift
register 0n
INTIICr
TSF0n
D5 D4 D3 D2 D1 D0
A
CK
Address
Shift operation
Address field transmission
SO0n bit manipulation
CKO0n
bit manipulation
Remark 0n = 00, r: IIC number (r = 00)

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