RL78/G10 CHAPTER 13 SERIAL INTERFACE IICA
R01UH0384EJ0311 Rev. 3.11 425
Dec 22, 2016
Figure 13-9. Format of IICA Control Register 01 (IICCTL01) (2/2)
CLD0 Detection of SCLA0 pin level (valid only when IICE0 = 1)
0 The SCLA0 pin was detected at low level.
1 The SCLA0 pin was detected at high level.
Condition for clearing (CLD0 = 0) Condition for setting (CLD0 = 1)
• When the SCLA0 pin is at low level
• When IICE0 = 0 (operation stop)
• Reset
• When the SCLA0 pin is at high level
DAD0 Detection of SDAA0 pin level (valid only when IICE0 = 1)
0 The SDAA0 pin was detected at low level.
1 The SDAA0 pin was detected at high level.
Condition for clearing (DAD0 = 0) Condition for setting (DAD0 = 1)
• When the SDAA0 pin is at low level
• When IICE0 = 0 (operation stop)
• Reset
• When the SDAA0 pin is at high level
SMC0 Operation mode switching
0 Operates in standard mode (fastest transfer rate: 100 kbps).
1 Operates in fast mode (fastest transfer rate: 400 kbps).
DFC0 Digital filter operation control
0 Digital filter off.
1 Digital filter on.
Use the digital filter only in fast mode and fast mode plus.
The digital filter is used for noise elimination.
The transfer clock does not vary, regardless of the DFC0 bit being set (1) or cleared (0).
Caution Note the minimum f
CLK operation frequency when setting the transfer clock.
The minimum f
CLK operation frequency for serial interface IICA is determined according to
the mode.
Normal mode: f
CLK = 1 MHz (min.)
Fast mode: f
CLK = 3.5 MHz (min.)
Remark IICE0: Bit 7 of IICA control register 00 (IICCTL00)
To Next Page
Loading...
Need help?
General
