Renesas RL78/G10 - Page 463

RL78/G10 CHAPTER 13 SERIAL INTERFACE IICA
R01UH0384EJ0311 Rev. 3.11 446
Dec 22, 2016
Figure 13-26. Communication Reservation Protocol
DI
SET1 STT0
Define communication
reservation
Wait
MSTS0 = 0?
(Communication reservation)
Note 2
Yes
No
(Generate start condition)
Cancel communication
reservation
MOV IICA0, #××H
EI
Sets STT0 flag (communication reservation)
Defines that communication reservation is in effect
(defines and sets user flag to any part of RAM)
Secures wait time
Note 1
by software.
Confirmation of communication reservation
Clear user flag
IICA0 write operation
Notes 1. The wait time (the number of cycles of f
CLK) is calculated as follows.
(IICWL0 setting value + IICWH0 setting value + 4) + tF × 2 × fCLK [clocks]
2. The communication reservation operation executes a write to the IICA shift register 0 (IICA0) when a
stop condition interrupt request occurs.
Remark STT0: Bit 1 of IICA control register 00 (IICCTL00)
MSTS0: Bit 7 of IICA status register 0 (IICS0)
IICA0: IICA shift register 0
IICWL0: IICA low-level width setting register 0
IICWH0: IICA high-level width setting register 0
tF: SDAA0 and SCLA0 signal falling times
f
CLK: CPU/peripheral hardware clock frequency