RL78/G10 CHAPTER 3 CPU ARCHITECTURE
R01UH0384EJ0311 Rev. 3.11 33
Dec 22, 2016
(d) In-service priority flags (ISP1, ISP0)
These flags manage the priority of acknowledgeable maskable vectored interrupts. Vectored interrupt requests
specified lower than the value of ISP0 and ISP1 flags by the priority specification flag registers (PR00L, PR00H,
PR10L, PR10H, PR01L, PR11L) (see 14.3.3 Priority specification flag registers (PR00L, PR00H, PR10L,
PR10H, PR01L, PR11L)) can not be acknowledged. Actual vectored interrupt request acknowledgment is
controlled by the interrupt enable flag (IE).
(e) Carry flag (CY)
This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out value upon
rotate instruction execution and functions as a bit accumulator during bit operation instruction execution.
(3) Stack pointer (SP)
This is a 16-bit register to hold the start address of the memory stack area. Only the internal RAM area can be set as
the stack area.
Figure 3-7. Format of Stack Pointer
15
SP SP15SP14SP13SP12SP11SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 0
0
In stack addressing through a stack pointer, the SP is decremented ahead of write (save) to the stack memory and is
incremented after read (restored) from the stack memory.
Cautions 1. Since reset signal generation makes the SP contents undefined, be sure to initialize the SP
before using the stack.
2. It is prohibited to use the general-purpose register (FFEF8H to FFEFFH) space for fetching
instructions or a stack area.
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