RL78/G10 CHAPTER 16 STANDBY FUNCTION
R01UH0384EJ0311 Rev. 3.11 532
Dec 22, 2016
(b) STOP mode release by reset signal generation
When the reset signal is generated, STOP mode is released, and then, as in the case with a normal reset
operation, the program is executed after branching to the reset vector address.
Figure 16-4. STOP Mode Release by Reset Signal Generation
(1) When high-speed on-chip oscillator clock is used as CPU clock
STOP
instruction
Reset signal
High-speed on-chip
oscillator clock
Normal operation
(
high-speed on-chip
oscillator
clock)
Normal operation
(
high-speed on-chip
oscillator
clock)
STOP mode
Reset
period
Oscillates
Oscillation
stopped
Status of CPU
Oscillates
Oscillation stopped
Wait for oscillation
accuracy stabilization
Reset processing
Note
(2) When high-speed system clock is used as CPU clock (16-pin products only)
STOP
instruction
Reset signal
High-speed
system clock
(X1 oscillation)
Normal operation
(high-speed
system clock)
STOP mode
Reset
period
Normal operation
(high-speed on-chip
oscillator clock)
Oscillates
Oscillation
stopped
Oscillates
Status of CPU
Oscillation stabilization time
(check by using OSTC register)
Starting X1 oscillation is
specified by software.
Oscillation
stopped
Oscillation stopped
Reset processing
Note
Note For the reset processing time, see CHAPTER 17 RESET FUNCTION.
For the reset processing time of the SPOR circuit, see CHAPTER 18 SELECTABLE POWER-ON-RESET
CIRCUIT.
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