RL78/G10 CHAPTER 23 INSTRUCTION SET
R01UH0384EJ0311 Rev. 3.11 569
Dec 22, 2016
Table 23-5. Operation List (2/17)
Notes 1. Number of CPU clocks (f
CLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or
when no data is accessed.
2. Number of CPU clocks (f
CLK) when the code flash memory is accessed.
Remark These numbers of clock cycles apply when the program is in the internal ROM (flash memory) area. When the
instruction is fetched from the internal RAM area, the number is, at most, the quadruple of the number given
here plus 6 further clock cycles.
Instruction
Group
Mnemonic Operands Bytes Clocks Clocks Flag
Note 1 Note 2 ZACCY
8-bit data
transfer
MOV A, sfr 2 1
−
A ← sfr
sfr, A 2 1
−
sfr ← A
A, [DE] 1 1 4 A ← (DE)
[DE], A 1 1
−
(DE) ← A
A, ES:[DE] 2 2 5 A ← (ES, DE)
ES:[DE], A 2 2
−
(ES, DE) ← A
A, [HL] 1 1 4 A ← (HL)
[HL], A 1 1
−
(HL) ← A
A, ES:[HL] 2 2 5 A ← (ES, HL)
ES:[HL], A 2 2
−
(ES, HL) ← A
A, [DE+byte] 2 1 4 A ← (DE + byte)
[DE+byte], A 2 1
−
(DE + byte) ← A
A, ES:[DE+byte] 3 2 5 A ← ((ES, DE) + byte)
ES:[DE+byte], A 3 2
−
((ES, DE) + byte) ← A
A, [HL+byte] 2 1 4 A ← (HL + byte)
[HL+byte], A 2 1
−
(HL + byte) ← A
A, ES:[HL+byte] 3 2 5 A ← ((ES, HL) + byte)
ES:[HL+byte], A 3 2
−
((ES, HL) + byte) ← A
A, [SP+byte] 2 1
−
A ← (SP + byte)
[SP+byte], A 2 1
−
(SP + byte) ← A
A, word[B] 3 1 4 A ← (B + word)
word[B], A 3 1
−
(B + word) ← A
A, ES:word[B] 4 2 5 A ← ((ES, B) + word)
ES:word[B], A 4 2
−
((ES, B) + word) ← A
A, word[C] 3 1 4 A ← (C + word)
word[C], A 3 1
−
(C + word) ← A
A, ES:word[C] 4 2 5 A ← ((ES, C) + word)
ES:word[C], A 4 2
−
((ES, C) + word) ← A
A, word[BC] 3 1 4 A ← (BC + word)
word[BC], A 3 1
−
(BC + word) ← A
A, ES:word[BC] 4 2 5 A ← ((ES, BC) + word)
ES:word[BC], A 4 2
−
((ES, BC) + word) ← A
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