Renesas RL78/G10 - Page 67

RL78/G10 CHAPTER 3 CPU ARCHITECTURE
R01UH0384EJ0311 Rev. 3.11 50
Dec 22, 2016
Figure 3-25. Example of [HL + byte], [DE + byte]
FFFFFH
F0000H
rp(HL/DE)
[HL + byte], [DE + byte]
Target
array
of data
Offset
Address of
an array
Other data in
the array
Target memory
Memory
Instruction code
OP-code
byte
<1> <2>
<2>
<1>
<2>
<1> <2>
Either pair of registers <1> specifies the address
where the target array of data starts in the 64-Kbyte
area from F0000H to FFFFFH.
“byte” <2> specifies an offset within the array to
the target location in memory.
Figure 3-26. Example of word[B], word[C]
F0000H
r(B/C)
FFFFFH
word [B], word [C]
OP-code
Low Addr.
High Addr.
Instruction code
Array of
word-sized
data
“word” <1> specifies the address where the target
array of word-sized data starts in the 64-Kbyte area
from F0000H to FFFFFH.
Either register <2> specifies an offset within the
array to the target location in memory.
Target memory
Memory
<1>
<1> <2> <1> <2>
<2>
<2>
Address of a word
within an array
Offset
Figure 3-27. Example of word[BC]
FFFFFH
F0000H
rp(BC)
word [BC]
OP-code
Low Addr.
High Addr.
Instruction code
Address of a word
within an array
Offset
Array of
word-sized
data
“word” <1> specifies the address where the target
array of word-sized data starts in the 64-Kbyte area
from F0000H to FFFFFH.
A pair of registers <2> specifies an offset within
the array to the target location in memory.
Target memory
Memory
<1>
<1>
<1> <2>
<2>
<2>