RL78/G10 CHAPTER 3 CPU ARCHITECTURE
R01UH0384EJ0311 Rev. 3.11 57
Dec 22, 2016
Figure 3-38. Example of RETI, RETB
RETI, RETB
SP
F0000H
PC
SP
PSW
Stack
area
Memory
(SP+3)
(SP+2)
SP+3
SP+2
(SP+1)
(SP)
SP+1
SP
SP+4
OP-code
<1>
<1>
Instruction code
<2>
<3>
Stack addressing is specified <1>.
The contents of addresses SP, SP + 1, SP + 2, and SP + 3 are
stored in PC bits 7 to 0, 15 to 8, 19 to 16, and the PSW, respectively
<2>.
The value of SP <3> is increased by four
.
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