Automationdirect.com DL05 - Math Instructions (Accumulator)

Appendix C
Inst. Execution Times
C–11
Instruction Execution Times
Timer, Counter, and Shift Register
DL05
Instruction Legal Data Types Execute Not Execute
SGCNT 1st 2nd
CT V:Data Reg.
V:Bit Reg.
K:Constant
P:Indir. (Data)
P:Indir. (Bit)
76.5 ms
76.5 ms
70.8 ms
106.8 ms
106.8 ms
75.3 ms
75.3 ms
69.6 ms
105.4 ms
105.4 ms
UDC 1st 2nd
CT V:Data Reg.
V:Bit Reg.
K:Constant
P:Indir. (Data)
P:Indir. (Bit)
118.3 ms
118.3 ms
111.8 m s
145.0 ms
145.0 ms
101.1 ms
101.1 ms
94.6 ms
128.0 ms
128.0 ms
SR C (N points to shift)
43.4ms+25.6msxN 31.4 ms
Accumulator / Stack Load and
Output Data Instructions
DL05
Instruction Legal Data Types Execute Not Execute
LD V:Data Reg.
V:Bit Reg.
K:Constant
P:Indir. (Data)
P:Indir. (Bit)
43.7 ms
43.7 ms
42.7 ms
68.7 ms
68.7 ms
3.7 ms
3.7 ms
3.7 ms
3.7 ms
3.7 ms
LDD V:Data Reg.
V:Bit Reg.
K:Constant
P:Indir. (Data)
P:Indir. (Bit)
47.1 ms
47.1 ms
42.8 ms
72.2 ms
72.2 ms
3.7 ms
3.7 ms
3.7 ms
3.7 ms
3.7 ms
LDF 1st 2nd
X, Y, C, S K:Constant
T, CT, SP (N pt)
65.8ms+13.9msxN 4.9 ms
LDA O: (Octal constant for address)
42.7 ms 3.7 ms
OUT V:Data Reg.
V:Bit Reg.
P:Indir. (Data)
P:Indir. (Bit)
16.6 ms
16.6 ms
41.8 ms
41.8 ms
3.7 ms
3.7 ms
3.7 ms
3.7 ms
OUTD V:Data Reg.
V:Bit Reg.
P:Indir. (Data)
P:Indir. (Bit)
18.1 ms
18.1 ms
43.3 ms
43.3 ms
3.8 ms
3.8 ms
3.8 ms
3.8 ms
OUTF 1st 2nd
X, Y, C K:Constant
(N pt)
61.9ms+22msxN 4.7 ms
POP None
41.1 ms 2.7 ms
Accumulator Data
Instructions