Automationdirect.com DL05 - Immediate Instructions; Timer, Counter, and Shift Register

Appendix C
Inst. Execution Times
C–10
Instruction Execution Times
Immediate Instructions
DL05
Instruction Legal Data Types Execute Not Execute
STRI X
38.2 ms 38.2 ms
STRNI X
38.5 ms 38.5 ms
ORI X
37.7 ms 37.7 ms
ORNI X
38.2 ms 38.2 ms
ANDI X
37.7 ms 37.7 ms
ANDNI X
38.1 ms 38.1 ms
OUTI Y
77.5 ms 77.5 ms
OROUTI Y
85.7 ms 85.7 ms
SETI 1st #: Y
2nd #: Y (N pt)
68.0 ms
108.5ms+1.6msxN
3.2 ms
4.3 ms
RSTI 1st #: Y
2nd #: Y (N pt)
66.9
10.8ms+1.7msxN
3.3 ms
4.4 ms
Timer, Counter, and Shift Register
DL05
Instruction Legal Data Types Execute Not Execute
TMR 1st 2nd
T V:Data Reg.
V:Bit Reg.
K:Constant
P:Indir. (Data)
P:Indir. (Bit)
64.0 ms
64.0 ms
58.1 ms
91.0 ms
91.0 ms
59.0 ms
59.0 ms
53.1 ms
86.0 ms
86.0 ms
TMRF 1st 2nd
T V:Data Reg.
V:Bit Reg.
K:Constant
P:Indir. (Data)
P:Indir. (Bit)
64.8 ms
64.8 ms
59.5 ms
92.5 ms
92.5 ms
57.3 ms
57.3 ms
52.0 ms
85.0 ms
85.0 ms
TMRA 1st 2nd
T V:Data Reg.
V:Bit Reg.
K:Constant
P:Indir. (Data)
P:Indir. (Bit)
72.2 ms
72.2 ms
65.7 ms
99.2 ms
99.2 ms
66.5 ms
66.5 ms
60.0 ms
93.5 ms
93.5 ms
TMRAF 1st 2nd
T V:Data Reg.
V:Bit Reg.
K:Constant
P:Indir. (Data)
P:Indir. (Bit)
71.4 ms
71.4 ms
65.2 ms
98.9 ms
98.9 ms
65.6 ms
65.6 ms
59.5 ms
93.1 ms
93.1 ms
CNT 1st 2nd
CT V:Data Reg.
V:Bit Reg.
K:Constant
P:Indir. (Data)
P:Indir. (Bit)
79.5 ms
79.5 ms
73.7 ms
107.0 ms
107.0 ms
66.9 ms
66.9 ms
61.1 ms
94.4 ms
94.4 ms
Immediate
Instructions
Timer, Counter,
and Shift Register