Automationdirect.com DL05 - Comparative Boolean Instructions

Appendix C
Inst. Execution Times
C–4
Instruction Execution Times
Comparative Boolean Instructions
DL05
Instruction Legal Data Types Execute Not Execute
STRE 1st 2nd
V: Data Reg. V:Data Reg.
V:Bit Reg.
K:Constant
P:Indir. (Data)
P:Indir. (Bit)
V: Bit Reg. V:Data Reg.
V:Bit Reg.
K:Constant
P:Indir. (Data)
P:Indir. (Bit)
P:Indir. (Data) V:Data Reg.
V:Bit Reg.
K:Constant
P:Indir. (Data)
P:Indir. (Bit)
P:Indir. (Bit) V:Data Reg.
V:Bit Reg.
K:Constant
P:Indir. (Data)
P:Indir. (Bit)
17.0 ms
17.0 ms
11.7 m s
42.8 ms
42.8 ms
17.0 ms
17.0 ms
11.7 m s
42.8 ms
42.8 ms
42.8 ms
42.8 ms
38.1 ms
66.8 ms
66.8 ms
42.8 ms
42.8 ms
38.1 ms
66.8 ms
66.8 ms
16.8 ms
16.8 ms
11.6 ms
42.7 ms
42.7 ms
16.8 ms
16.8 ms
11.6 ms
42.7 ms
42.7 ms
42.7 ms
42.7 ms
38.0 ms
66.7 ms
66.7 ms
42.7 ms
42.7 ms
38.0 ms
66.7 ms
66.7 ms
STRNE 1st 2nd
V: Data Reg. V:Data Reg.
V:Bit Reg.
K:Constant
P:Indir. (Data)
P:Indir. (Bit)
V: Bit Reg. V:Data Reg.
V:Bit Reg.
K:Constant
P:Indir. (Data)
P:Indir. (Bit)
P:Indir. (Data) V:Data Reg.
V:Bit Reg.
K:Constant
P:Indir. (Data)
P:Indir. (Bit)
P:Indir. (Bit) V:Data Reg.
V:Bit Reg.
K:Constant
P:Indir. (Data)
P:Indir. (Bit)
17.1 ms
17.1 ms
11.8 m s
43.0 ms
43.0 ms
17.1 ms
17.1 ms
11.8 m s
43.0 ms
43.0 ms
43.0 ms
43.0 ms
38.2 ms
67.0 ms
67.0 ms
43.0 ms
43.0 ms
38.2 ms
67.0 ms
67.0 ms
17.3 ms
17.3 ms
12.0 ms
43.1 ms
43.1 ms
17.3 ms
17.3 ms
12.0 ms
43.1 ms
43.1 ms
43.1 ms
43.1 ms
38.4 ms
67.1 ms
67.1 ms
43.1 ms
43.1 ms
38.4 ms
67.1 ms
67.1 ms
Comparative
Boolean
Instructions