Automationdirect.com DL05 - Logical Instructions; Math Instructions

Appendix C
Inst. Execution Times
C–12
Instruction Execution Times
Logical (Accumulator) Instructions
DL05
Instruction Legal Data Types Execute Not Execute
AND V:Data Reg.
V:Bit Reg.
P:Indir. (Data)
P:Indir. (Bit)
23.5 ms
23.5 ms
48.3 ms
48.3 ms
3.9 ms
3.9 ms
3.9 ms
3.9 ms
ANDD V:Data Reg.
V:Bit Reg.
K:Constant
P:Indir. (Data)
P:Indir. (Bit)
23.3 ms
23.3 ms
19.0 ms
48.3 ms
48.3 ms
3.7 ms
3.7 ms
3.9 ms
3.9 ms
3.9 ms
OR V:Data Reg.
V:Bit Reg.
P:Indir. (Data)
P:Indir. (Bit)
23.9 ms
23.9 ms
48.8 ms
48.8 ms
3.7 ms
3.7 ms
3.8 ms
3.8 ms
ORD V:Data Reg.
V:Bit Reg.
K:Constant
P:Indir. (Data)
P:Indir. (Bit)
23.8 ms
23.8 ms
19.4 ms
48.6 ms
48.6 ms
3.8 ms
3.8 ms
3.7 ms
3.7 ms
3.7 ms
XOR V:Data Reg.
V:Bit Reg.
P:Indir. (Data)
P:Indir. (Bit)
23.5 ms
23.5 ms
48.3 ms
48.3 ms
3.9 ms
3.9 ms
3.9 ms
3.9 ms
XORD V:Data Reg.
V:Bit Reg.
K:Constant
P:Indir. (Data)
P:Indir. (Bit)
23.3 ms
23.3 ms
19.0 ms
48.3 ms
48.3 ms
3.7 ms
3.7 ms
3.9 ms
3.9 ms
3.9 ms
CMP V:Data Reg.
V:Bit Reg.
P:Indir. (Data)
P:Indir. (Bit)
25.4 ms
25.4 ms
50.0 ms
50.0 ms
3.7 ms
3.7 ms
3.7 ms
3.7 ms
CMPD V:Data Reg.
V:Bit Reg.
K:Constant
P:Indir. (Data)
P:Indir. (Bit)
37.3 ms
37.3 ms
32.7 ms
62.0 ms
62.0 ms
3.9 ms
3.9 ms
3.7 ms
3.8 ms
3.8 ms
Math Instructions (Accumulator)
DL05
Instruction Legal Data Types Execute Not Execute
ADD V:Data Reg.
V:Bit Reg.
P:Indir. (Data)
P:Indir. (Bit)
140.7 ms
140.7 ms
185.1 ms
185.1 ms
3.7 ms
3.7 ms
3.7 ms
3.7 ms
ADDD V:Data Reg.
V:Bit Reg.
K:Constant
P:Indir. (Data)
P:Indir. (Bit)
152.4 ms
152.4 ms
123.2 ms
193.5 ms
193.5 ms
3.9 ms
3.9 ms
3.7 ms
3.7 ms
3.7 ms
SUB V:Data Reg.
V:Bit Reg.
P:Indir. (Data)
P:Indir. (Bit)
148.1 ms
148.1 ms
192.7 ms
192.7 ms
3.7 ms
3.7 ms
3.7 ms
3.7 ms
Logical
Instructions
Math Instructions