Automationdirect.com DL05 - Page 451

Appendix C
Inst. Execution Times
C–9
Instruction Execution Times
Comparative Boolean (cont.)
DL05
Instruc Legal Data Types Execute Not Execute
AND 1st 2nd
T, CT V:Data Reg.
V:Bit Reg.
K:Constant
P:Indir. (Data)
P:Indir. (Bit)
15.6 ms
15.6 ms
10.9 ms
41.6 ms
41.6 ms
15.6 ms
15.6 ms
10.9 ms
41.6 ms
41.6 ms
1st 2nd
V: Data Reg. V:Data Reg.
V:Bit Reg.
K:Constant
P:Indir. (Data)
P:Indir. (Bit)
V: Bit Reg. V:Data Reg.
V:Bit Reg.
K:Constant
P:Indir. (Data)
P:Indir. (Bit)
P:Indir. (Data) V:Data Reg.
V:Bit Reg.
K:Constant
P:Indir. (Data)
P:Indir. (Bit)
P:Indir. (Bit) V:Data Reg.
V:Bit Reg.
K:Constant
P:Indir. (Data)
P:Indir. (Bit)
15.6 ms
15.6 ms
10.9 ms
41.6 ms
41.6 ms
15.6 ms
15.6 ms
10.9 ms
41.6 ms
41.6 ms
41.6 ms
41.6 ms
36.9 ms
65.6 ms
65.6 ms
41.6 ms
41.6 ms
36.9 ms
65.6 ms
65.6 ms
15.6 ms
15.6 ms
10.9 ms
41.6 ms
41.6 ms
15.6 ms
15.6 ms
10.9 ms
41.6 ms
41.6 ms
41.6 ms
41.6 ms
36.9 ms
65.6 ms
65.6 ms
41.6 ms
41.6 ms
36.9 ms
65.6 ms
65.6 ms
ANDN 1st 2nd
T, CT V:Data Reg.
V:Bit Reg.
K:Constant
P:Indir. (Data)
P:Indir. (Bit)
15.8 ms
15.8 ms
10.8 ms
41.9 ms
41.9 ms
15.7
15.7
10.8
41.9
41.9
1st 2nd
V: Data Reg. V:Data Reg.
V:Bit Reg.
K:Constant
P:Indir. (Data)
P:Indir. (Bit)
V: Bit Reg. V:Data Reg.
V:Bit Reg.
K:Constant
P:Indir. (Data)
P:Indir. (Bit)
P:Indir. (Data) V:Data Reg.
V:Bit Reg.
K:Constant
P:Indir. (Data)
P:Indir. (Bit)
P:Indir. (Bit) V:Data Reg.
V:Bit Reg.
K:Constant
P:Indir. (Data)
P:Indir. (Bit)
15.8 ms
15.8 ms
10.8 ms
41.9 ms
41.9 ms
15.8 ms
15.8 ms
10.8 ms
41.9 ms
41.9 ms
41.8 ms
41.8 ms
37.8 ms
65.9 ms
65.9 ms
41.8 ms
41.8 ms
37.8 ms
65.9 ms
65.9 ms
15.7 ms
15.7 ms
10.8 ms
41.9 ms
41.9 ms
15.7 ms
15.7 ms
10.8 ms
41.9 ms
41.9 ms
41.8 ms
41.8 ms
37.8 ms
65.9 ms
65.9 ms
41.8 ms
41.8 ms
37.8 ms
65.9 ms
65.9 ms