Automationdirect.com DL05 - Page 450

Appendix C
Inst. Execution Times
C–8
Instruction Execution Times
Comparative Boolean (cont.)
DL05
Instruc Legal Data Types Execute Not Execute
OR 1st 2nd
T, CT V:Data Reg.
V:Bit Reg.
K:Constant
P:Indir. (Data)
P:Indir. (Bit)
16.6 ms
16.6 ms
11.5 m s
42.6 ms
42.6 ms
16.5 ms
16.5 ms
11.4 ms
42.5 ms
42.5 ms
1st 2nd
V: Data Reg. V:Data Reg.
V:Bit Reg.
K:Constant
P:Indir. (Data)
P:Indir. (Bit)
V: Bit Reg. V:Data Reg.
V:Bit Reg.
K:Constant
P:Indir. (Data)
P:Indir. (Bit)
P:Indir. (Data) V:Data Reg.
V:Bit Reg.
K:Constant
P:Indir. (Data)
P:Indir. (Bit)
P:Indir. (Bit) V:Data Reg.
V:Bit Reg.
K:Constant
P:Indir. (Data)
P:Indir. (Bit)
16.6 ms
16.6 ms
11.5 m s
42.6 ms
42.6 ms
16.6 ms
16.6 ms
11.5 m s
42.6 ms
42.6 ms
42.6 ms
42.6 ms
37.7 ms
66.5 ms
66.5 ms
42.6 ms
42.6 ms
37.7 ms
66.5 ms
66.5 ms
16.5 ms
16.5 ms
11.4 ms
42.5 ms
42.5 ms
16.5 ms
16.5 ms
11.4 ms
42.5 ms
42.5 ms
42.5 ms
42.5 ms
37.6 ms
66.4 ms
66.4 ms
42.5 ms
42.5 ms
37.6 ms
66.4 ms
66.4 ms
ORN 1st 2nd
T, CT V:Data Reg.
V:Bit Reg.
K:Constant
P:Indir. (Data)
P:Indir. (Bit)
15.8 ms
15.8 ms
10.8 ms
41.9 ms
41.9 ms
15.8 ms
15.8 ms
10.8 ms
41.9 ms
41.9 ms
1st 2nd
V: Data Reg. V:Data Reg.
V:Bit Reg.
K:Constant
P:Indir. (Data)
P:Indir. (Bit)
V: Bit Reg. V:Data Reg.
V:Bit Reg.
K:Constant
P:Indir. (Data)
P:Indir. (Bit)
P:Indir. (Data) V:Data Reg.
V:Bit Reg.
K:Constant
P:Indir. (Data)
P:Indir. (Bit)
P:Indir. (Bit) V:Data Reg.
V:Bit Reg.
K:Constant
P:Indir. (Data)
P:Indir. (Bit)
15.8 ms
15.8 ms
10.8 ms
41.9 ms
41.9 ms
15.8 ms
15.8 ms
10.8 ms
41.9 ms
41.9 ms
41.8 ms
41.8 ms
37.1 ms
65.9 ms
65.9 ms
41.8 ms
41.8 ms
37.1 ms
65.9 ms
65.9 ms
15.8 ms
15.8 ms
10.8 ms
41.9 ms
41.9 ms
15.8 ms
15.8 ms
10.8 ms
41.9 ms
41.9 ms
41.8 ms
41.8 ms
37.1 ms
65.9 ms
65.9 ms
41.8 ms
41.8 ms
37.1 ms
65.9 ms
65.9 ms