Keysight U8903B - Figure 3-59 Digital Generator > Output Config > Sync Clock Menu Page; Sync Clock; Table 3-31 Digital Generator > Output Config > Sync Clock Menu Description

Audio Generator Functions 3
Keysight U8903B User’s Guide 145
Sync clock
Figure 3-59 Digital Generator > Output Config > Sync Clock menu page
Table 3-31 Digital Generator > Output Config > Sync Clock menu description
Menu Description
Output Press the Output softkey to enable or disable the synchronous clock output.
Source
Press the Source softkey to select the synchronous clock source. Refer to “Appendix 20: Digital System Clock
Distribution Block Diagram” on page 565 for more information on the system clock.
–Internal
– AES RCLK
–External
Divider
Press the Divider softkey to select the synchronous clock divider value. When the synchronous clock divider is set to 1, the
synchronous clock is locked to 128 × sampling rate (bi-phase clock). When the synchronous clock divider is set to 128, the
synchronous clock is divided by 128 which is equal to the sampling rate set at the U8903B.
–1
–128