Keysight U8903B - Appendix 20: Digital System Clock Distribution Block Diagram

Appendixes A
Keysight U8903B User’s Guide 565
Appendix 20: Digital System Clock Distribution Block Diagram
The digital system clock distribution block diagram is shown in Figure A-3.
Figure A-3 Digital system clock distribution block diagram
PLL
AES Receiver
PLL
PLL
PLL
Internal clock
Recovered Master Clock
Master Clock / Frame Sync In
DSI Generator Frame Sync
Generator Reference Clock
Bit Clock
Master Clock
Sync Clock
PLL = Phase-Locked Loop
DSI Generator Bit Clock