Renesas RL78/G10 - Page 10

Index-5
CHAPTER 7 12-BIT INTERVAL TIMER ................................................................................................ 224
7.1 Functions of 12-bit Interval Timer ............................................................................................. 224
7.2 Configuration of 12-bit Interval Timer ...................................................................................... 224
7.3 Registers Controlling 12-bit Interval Timer ............................................................................. 225
7.3.1 Peripheral enable register 0 (PER0) ............................................................................................... 225
7.3.2 Operation speed mode control register (OSMC) ............................................................................ 226
7.3.3 Interval timer control register (ITMCH, ITMCL) ............................................................................... 227
7.4 12-bit Interval Timer Operation ................................................................................................. 228
7.4.1 12-bit interval timer operation timing .............................................................................................. 228
7.4.2 Start of count operation and re-enter to HALT/STOP mode after returned
from HALT/STOP mode ............................................................................................................... 229
CHAPTER 8 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER ................................................. 230
8.1 Functions of Clock Output/Buzzer Output Controller ............................................................ 230
8.2 Configuration of Clock Output/Buzzer Output Controller ...................................................... 231
8.3 Registers Controlling Clock Output/Buzzer Output Controller ............................................. 231
8.3.1 Clock output select register 0 (CKS0) ............................................................................................ 232
8.3.2 Registers controlling port functions of clock output/buzzer output pin ............................................ 233
8.4 Operations of Clock Output/Buzzer Output Controller .......................................................... 234
8.4.1 Operation as output pin .................................................................................................................. 234
CHAPTER 9 WATCHDOG TIMER ....................................................................................................... 235
9.1 Functions of Watchdog Timer ................................................................................................... 235
9.2 Configuration of Watchdog Timer ............................................................................................ 236
9.3 Register Controlling Watchdog Timer ...................................................................................... 237
9.3.1 Watchdog timer enable register (WDTE) ........................................................................................ 237
9.4 Operation of Watchdog Timer ................................................................................................... 238
9.4.1 Controlling operation of watchdog timer ......................................................................................... 238
9.4.2 Setting time of watchdog timer ....................................................................................................... 239
CHAPTER 10 A/D CONVERTER ......................................................................................................... 240
10.1 Function of A/D Converter ....................................................................................................... 240
10.2 Configuration of A/D Converter .............................................................................................. 242
10.3 Registers Used in A/D Converter ............................................................................................ 243
10.3.1 Peripheral enable register 0 (PER0) ............................................................................................. 244
10.3.2 A/D converter mode register 0 (ADM0) ........................................................................................ 245
10.3.3 A/D converter mode register 2 (ADM2) ........................................................................................ 249
10.3.4 A/D conversion result higher-order bit storage register (ADCRH) ................................................ 249
10.3.5 A/D conversion result lower-order bit storage register (ADCRL) .................................................. 250
10.3.6 Analog input channel specification register (ADS) ........................................................................ 251