RL78/G10 CHAPTER 6 TIMER ARRAY UNIT
R01UH0384EJ0311 Rev. 3.11 145
Dec 22, 2016
(4) One-count mode operation
<1> Operation is enabled (TE0n = 1) by writing 1 to the TS0n bit.
<2> Timer count register 0n (TCR0n) holds the initial value until start trigger generation.
<3> Rising edge of the TI0n input is detected.
<4> On start trigger detection, the value of timer data register 0n (TDR0n) is loaded to the TCR0n register and
count starts.
<5> When the TCR0n register counts down and its count value is 0000H, the interrupt request signal
(INTTM0n) is generated and the value of the TCR0n register becomes FFFFH and counting stops.
Figure 6-27. Operation Timing (In One-count Mode)
Remark Figure 6-27 shows the timing when the noise filter is not used. When the noise filter is on-state, the edge
detection is delayed by two cycles of the operating clock (f
MCK) from the TI0n input (totally 3 to 4 cycles).
The error of one cycle is due to the asynchronous timing between the TI0n input and operating clock
(f
MCK).
fMC
(fTCLK)
TS0n (Write)
TE0n
TI0n input
<1>
<2>
Rising edge
Edge detection
<4>
TCR0n
Initial value
1
Start trigger
detection signal
<3>
m
0
FFFF
INTTM0n
Start trigger input wait status
<5>
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