RL78/G10 CHAPTER 6 TIMER ARRAY UNIT
R01UH0384EJ0311 Rev. 3.11 152
Dec 22, 2016
Figure 6-34. Set/Reset Timing Operating Statuses
(a) Basic operation timing
(b) Operation timing when 0 % duty
Remarks 1. Internal reset signal: TO0n pin reset/toggle signal
Internal set signal: TO0n pin set signal
2. n: Master channel number (for 10-pin products, n = 0; for 16-pin products, n = 0, 2)
p: Slave channel number (n < p ≤ 3)
TO0n pin
TO0n
INTTM0p
fTCLK
INTTM0n
Internal reset
signal
Internal set
signal
Internal reset
signal
TO0p pin
TO0p
Master
channel
Slave
channel
1 clock delay
Toggle
Toggle
Set
Set
Reset
Reset has priority.
Reset
Reset has priority.
TCR0p
0000
0001
0000
0001
TO0n pin
TO0n
INTTM0p
fTCLK
INTTM0n
Internal reset
signal
Internal reset
signal
TO0p pin
TO0p
Master
channel
Slave
channel
1 clock delay
Toggle Toggle
Set
Set
Reset
Internal set
signal
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