RL78/G10 CHAPTER 6 TIMER ARRAY UNIT
R01UH0384EJ0311 Rev. 3.11 166
Dec 22, 2016
Figure 6-46. Example of Set Contents of Registers in External Event Counter Mode (2/2)
(d) Timer output level register 0 (TOL0)
Bit n
TOL0
TOL0n
0
0: Setting is invalid because master channel output mode is set (TOM0n = 0).
(e) Timer output mode register 0 (TOM0)
Bit n
TOM0
TOM0n
0
0: Sets master channel output mode.
Remark n: Channel number
n = 0, 1 (for 10-pin products); n = 0 to 3 (for 16-pin products)
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