Renesas RL78/G10 - Page 202

RL78/G10 CHAPTER 6 TIMER ARRAY UNIT
R01UH0384EJ0311 Rev. 3.11 185
Dec 22, 2016
Figure 6-62. Example of Set Contents of Registers to Delay Counter (1/2)
(a) Timer mode register 0n (TMR0nH, TMR0nL)
TMR0nH TMR0nL
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
TMR0n
CKS0n1
1/0 0 0
CCS0n
0
M/S
Note1
0/1
STS0n2
0
STS0n1
0
STS0n0
1
CIS0n1
1/0
CIS0n0
1/0 0 0
MD0n3
1
MD0n2
0
MD0n1
0
MD0n0
1/0
Operation mode of channel n
100B: One-count mode
Start trigger during operation
0: Trigger input is invalid.
1: Trigger input is valid.
Selection of TI0n pin input edge
00B: Detects falling edge.
01B: Detects rising edge.
10B: Detects both edges.
11B: Setting prohibited
Start trigger selection
001B: Selects the TI0n pin input valid edge.
Note2
Setting of MASTER0n bit (Channel 2)
0: Independent channel operation
Setting of SPLIT0n bit (Channel 1, 3)
0: 16-bit timer
1: 8-bit timer
Count clock selection
0: Selects operation clock (f
MCK).
Operation clock (f
MCK) selection
0: Selects CK00 as operation clock of channel n.
1: Selects CK02 as operation clock of channel n.
(b) Timer output register 0 (TO0)
Bit n
TO0
TO0n
0
0: Outputs 0 from TO0n.
(c) Timer output enable register 0 (TOE0)
Bit n
TOE0
TOE0n
0
0: Stops the TO0n output operation by counting operation.
Notes 1. TMR02: MASTER0n bit
TMR01, TMR03: SPLIT0n bit
TMR00: 0 fixed
2. A software operation (TS0n = 1) can be used as a capture trigger, instead of using the TI0n pin input.
Remark n: Channel number
n = 0, 1 (for 10-pin products); n = 0 to 3 (for 16-pin products)