RL78/G10 CHAPTER 12 SERIAL ARRAY UNIT
R01UH0384EJ0311 Rev. 3.11 380
Dec 22, 2016
Figure 12-80. Procedure for Resuming UART Reception
Wait until the communication target stops
or communication finishes.
Re-set the register to change the operation
clock setting.
Re-set the register to change the transfer
baud rate setting (setting the transfer clock
by dividing the operation clock (f
MCK)).
Re-set the registers to change serial mode
registers 0n, 0r (SMR0nH/L, SMR0rH/L)
setting.
Set the SS0n bit of the target channel to 1 and set
the SE0n bit to 1 (to enable operation). Become
wait for start bit detection.
(Selective)
Re-set the register to change serial
communication operation setting register
0n (SCR0nH/L) setting.
If the FEF, PEF, and OVF flags remain
set, clear them using serial flag clear
trigger register 0n (SIR0n).
(Essential)
(Selective)
(Selective)
(Selective)
(Selective)
Enable data input of the target channel
by setting a port register and a port mode
register.
(Essential)
Starting setting for resumption
Changing setting of the SPS0 register
Changing setting of the SDR0nH register
Writing to the SS0 register
Completing resumption setting
Changing setting of the SCR0nH/L register
Clearing error flag
Changing setting of the SMR0nH/L
and SMR0rH/L registers
Setting port
(Essential)
Ye s
No
Preparing the communication
target completed?
Caution After setting the RXE0n bit of SCR0n register to 1, be sure to set SS0n to 1 after 4 or more f
CLK
clocks have elapsed.
Remark If PER0 is rewritten while stopping the master transmission and the clock supply is stopped, wait until
the transmission target (slave) stops or transmission finishes, and then perform initialization instead of
restarting the transmission.
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