RL78/G10 CHAPTER 13 SERIAL INTERFACE IICA
R01UH0384EJ0311 Rev. 3.11 418
Dec 22, 2016
Figure 13-6. Format of IICA Control Register 00 (IICCTL00) (3/4)
STT0
Notes 1, 2
Start condition trigger
0 Do not generate a start condition.
1 When bus is released (in standby state, when IICBSY = 0):
If this bit is set (1), a start condition is generated (startup as the master).
When a third party is communicating:
• When communication reservation function is enabled (IICRSV = 0)
Functions as the start condition reservation flag. When set to 1, automatically generates a start
condition after the bus is released.
• When communication reservation function is disabled (IICRSV = 1)
Even if this bit is set (1), the STT0 bit is cleared and the STT0 clear flag (STCF) is set (1). No start
condition is generated.
In the wait state (when master device):
Generates a restart condition after releasing the wait.
Cautions concerning set timing
• For master reception: Cannot be set to 1 during transfer. Can be set to 1 only in the waiting period when the
ACKE0 bit has been cleared to 0 and slave has been notified of final reception.
• For master transmission: A start condition cannot be generated normally during the acknowledge period. Set to 1
during the wait period that follows output of the ninth clock.
• Cannot be set to 1 at the same time as stop condition trigger (SPT0).
• Setting the STT0 bit to 1 and then setting it again before it is cleared condition is prohibited.
Condition for clearing (STT0 = 0) Condition for setting (STT0 = 1)
• Cleared by setting the STT0 bit to 1 while
communication reservation is prohibited.
• Cleared by loss in arbitration
• Cleared after start condition is generated by master
device
• Cleared by LREL0 = 1 (exit from communications)
• When IICE0 = 0 (operation stop)
• Reset
• Set by instruction
Notes 1. The signal of this bit is invalid while IICE0 is 0.
2. When the STT0 bit is read, 0 is always read.
Remark IICRSV0: Bit 0 of IIC flag register 0 (IICF0)
STCF0: Bit 7 of IIC flag register 0 (IICF0)
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