RL78/G10 CHAPTER 13 SERIAL INTERFACE IICA
R01UH0384EJ0311 Rev. 3.11 419
Dec 22, 2016
Figure 13-6. Format of IICA Control Register 00 (IICCTL00) (4/4)
SPT0
Note
Stop condition trigger
0 Stop condition is not generated.
1 Stop condition is generated (termination of master device’s transfer).
Cautions concerning set timing
• For master reception: Cannot be set to 1 during transfer.
Can be set to 1 only in the waiting period when the ACKE0 bit has been cleared to 0 and
slave has been notified of final reception.
• For master transmission: A stop condition cannot be generated normally during the acknowledge period.
Therefore, set to 1 during the wait period that follows output of the ninth clock.
• Cannot be set to 1 at the same time as start condition trigger (STT0).
• The SPT0 bit can be set to 1 only when in master mode.
• When the WTIM0 bit has been cleared to 0, if the SPT0 bit is set to 1 during the wait period that follows output of
eight clocks, note that a stop condition will be generated during the high-level period of the ninth clock. The WTIM0
bit should be changed from 0 to 1 during the wait period following the output of eight clocks, and the SPT0 bit should
be set to 1 during the wait period that follows the output of the ninth clock.
• Setting the SPT0 bit to 1 and then setting it again before it is cleared condition is prohibited.
Condition for clearing (SPT0 = 0) Condition for setting (SPT0 = 1)
• Cleared by loss in arbitration
• Automatically cleared after stop condition is detected
• Cleared by LREL0 = 1 (exit from communications)
• When IICE0 = 0 (operation stop)
• Reset
• Set by instruction
Note When the SPT0 bit is read, 0 is always read.
Caution When bit 3 (TRC0) of the IICA status register 0 (IICS0) is set to 1 (transmission status), bit 5
(WREL0) of IICA control register 00 (IICCTL00) is set to 1 during the ninth clock and wait is
canceled, after which the TRC0 bit is cleared (reception status) and the SDAA0 line is set to
high impedance. Release the wait performed while the TRC0 bit is 1 (transmission status)
by writing to the IICA shift register 0.
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