RL78/G10 CHAPTER 13 SERIAL INTERFACE IICA
R01UH0384EJ0311 Rev. 3.11 488
Dec 22, 2016
The following describes the operations in Figure 13-31 (4) Data ~ restart condition ~ address. After the operations
in steps <7> and <8>, the operations in steps <1> to <3> are performed. These steps return the processing to step
<3>, the data transmission step.
<7> After data transfer is completed, because of ACKE0 = 1, the slave device sends an ACK by hardware to the
master device. The ACK is detected by the master device (ACKD0 = 1) at the rising edge of the 9th clock.
<8> The master device and slave device set a wait status (SCLA0 = 0) at the falling edge of the 9th clock, and
both the master device and slave device issue an interrupt (INTIICA0: end of transfer).
<i> The slave device reads the received data and releases the wait status (WREL0 = 1).
<ii> The start condition trigger is set again by the master device (STT0 = 1) and a start condition (i.e. SCLA0 =1
changes SDAA0 from 1 to 0) is generated once the bus clock line goes high (SCLA0 = 1) and the bus data
line goes low (SDAA0 = 0) after the restart condition setup time has elapsed. When the start condition is
subsequently detected, the master device is ready to communicate once the bus clock line goes low
(SCLA0 = 0) after the hold time has elapsed.
<iii> The master device writing the address + R/W (transmission) to the IICA shift register (IICA0) enables the
slave address to be transmitted.
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