RL78/G10 APPENDIX A REVISION HISTORY
R01UH0384EJ0311 Rev. 3.11 613
Dec 22, 2016
(5/9)
Edition
Description Chapter
Rev.2.00
Addition of description of 16-pin products
CHAPTER 12
SERIAL ARRAY UNIT
Modification of description in Figure 12-1 Block Diagram of Serial Array Unit 0
Modification of description in (2) Serial data register 0nL (SDR0nL)
Modification of caution in Figure 12-5 Format of Serial Mode Register 0n (SMR0nH,
SMR0nL) (1/2)
Modification of caution in Figure 12-5 Format of Serial Mode Register 0n (SMR0nH,
SMR0nL) (2/2)
Modification of caution in Figure 12-6 Format of Serial Mode Register 0n (SCR0nH,
SCR0nL) (1/2)
Modification of description in 12.3.5 Serial data register 0n (SDR0nH, SDR0nL)
Modification of caution in Figure 12-8 Format of Serial Flag Clear Trigger Register 0n
(SIR0n)
Modification of caution in Figure 12-13 Format of Serial Output Enable Register 0 (SOE0)
Modification of caution in Figure 12-14 Format of Serial Output Register 0 (SO0)
Modification of caution in Figure 12-15 Format of Serial Clock Output Register (CKO0)
Modification of description in 12.3.16 Input switch control register (ISC)
Modification of description in 12.3.17 Registers controlling port functions of serial
input/output pins
Modification of cautions 1 and 2 in Figure 12-20 Peripheral Enable Register 0 (PER0)
Setting When Stopping Operation by Units
Addition of description in 12.5 Operation of 3-Wire Serial I/O (CSI00, CSI01)
Communication
Modification of notes 1 to 3 in 12.5.4 Slave transmission
Modification of note in Table 12-3 Selection of Operation Clock For UART
Addition of description in 12.7 Operation of Simplified I2C (IIC00) Communication
Addition of Figure 12-98 Processing Procedure in Case of Overrun Error
Modification of description in Figure 13-1 Block Diagram of Serial Interface IICA
CHAPTER 13
SERIAL INTERFACE IICA
Modification of note in Figure 13-4 Format of Slave Address Register 0 (SVA0)
Modification of cautions 1 and 2 in Figure 13-5 Format of Peripheral Enable Register 0
(PER0)
Addition of note 2 in Figure 13-6 Format of IICA Control Register 00 (IICCTL00) (3/4)
Addition of note in Figure 13-6 Format of IICA Control Register 00 (IICCTL00) (4/4)
Modification of description in Figure 13-9 Format of IICA Control Register 01 (IICCTL01)
(2/2)
Modification of description in 13.3.8 Registers controlling port functions of IICA serial
input/output pins
Modification of description in Figure 13-22 Flow When Setting WUP0 = 0 upon Address
Match (Including Extension Code Reception)
Modification of description in (3) If other I2C communications are already in progress
Modification of description in Figure 13-27 Master Operation in Single-Master System
Modification of description in Figure 13-28 Master Operation in Multi-Master System (2/3)
and (3/3)
Modification of description in Figure 13-29 Slave Operation Flowchart (1)
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