RL78/G10 APPENDIX A REVISION HISTORY
R01UH0384EJ0311 Rev. 3.11 615
Dec 22, 2016
(7/9)
Edition
Description Chapter
Rev.2.00
Modification of description and notes 1 to 6 in 24.6.1 A/D converter characteristics
CHAPTER 24
ELECTRICAL
SPECIFICATIONS
Addition of description, notes 1 and 2 in 24.6.2 Comparator characteristics
Addition of description and note in 24.6.3 Internal reference voltage characteristics
Addition of caution in 24.6.4 SPOR Circuit characteristics
Addition of figure in 24.6.6 Data retention power supply voltage characteristics
Addition of R5F10Y17ASP in 25.1 10-pin products
CHAPTER 25
PACKAGE DRAWINGS
Modification of package drawing in 25.2 16-pin products
Rev.1.00
Modification of description of the power supply voltage in 1.1 Features
CHAPTER 1
OUTLINE
Modification of Figure 1-1 Classification of Part Number
Modification of description in 1.6 Outline of Functions and addition of note
Modification of error in 2.1.2 16-pin products
CHAPTER 2
PIN FUNCTIONS
Modification of 2.2.2 Description of functions
Addition of caution in Figure 3-1 Memory Map for the R5F10Y14ASP and R5F10Y44ASP
to Figure 3-3 Memory Map for the R5F10Y47ASP
CHAPTER 3
CPU ARCHITECTURE
Modification of error in Figure 3-7 Format of Stack Pointer
Modification of error in 4.2.1 Port 0
CHAPTER 4
PORT FUNCTIONS
Modification of error in Figure 4-4 Format of Port Output Mode Register 0 (POM0)
Addition of caution in Figure 4-6 Format of Peripheral I/O Redirection Register (PIOR)
Modification of error in Table 4-5 Examples of Register And Output Latch Settings With
Pin Functions (1/4)
Modification of error in Table 4-5 Examples of Register And Output Latch Settings With
Pin Functions (2/4)
Addition of note in 5.1 Functions of Clock Generator
CHAPTER 5
CLOCK GENERATOR
Modification of error in 5.3.1 Clock operation mode control register (CMC)
Modification of error in 5.3.3 Clock operation status control register (CSC)
Modification of description in Figure 5-5 Format of Oscillation Stabilization Time Counter
Status Register (OSTC)
Modification of description in Figure 5-6 Format of Oscillation Stabilization Time Select
Register (OSTS)
Modification of value after reset in Figure 5-9 Format of High-Speed On-Chip Oscillator
Frequency Selection Register (HOCODIV)
Addition of note in 5.5 Clock Generator Operation
Modification of Figure 5-12 Clock Generator Operation When Power Supply Voltage Is
Turned On
Modification of 5.6.2 Example of setting X1 oscillation clock
Modification of Figure 5-13 CPU Clock Status Transition Diagram
Modification of remark in Table 5-5 Maximum Number of Clocks Required for fIH ↔ fMX
Modification of description of the timer array unit function in the beginning of the chapter
CHAPTER 6
TIMER ARRAY UNIT
Addition of caution in Figure 6-3 Format of Timer/Counter Register 0n (TCR0n) (n = 0 to
3)
Addition of caution in Table 6-3 Timer/counter Register 0n (TCR0n) Read Value in
Various Operation Modes
Modification of description in 6.2.2 Timer data register 0n (TDR0n) and addition of caution
Modification of description in Figure 6-7 Format of Timer Clock Select Register 0 (TPS0)
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