Reset and clock control (RCC) RM0401
104/771 RM0401 Rev 3
5.3.2 RCC PLL configuration register (RCC_PLLCFGR)
Address offset: 0x04
Reset value: 0x7F00 3010
Access: no wait state, word, half-word and byte access.
This register is used to configure the PLL clock outputs according to the formulas:
• f
(VCO clock)
= f
(PLL clock input)
× (PLLN / PLLM)
• f
(PLL general clock output)
= f
(VCO clock)
/ PLLP
• f
(I2S, System)
= f
(VCO clock)
/ PLLR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. PLLR3 PLLR2 PLLR1 PLLQ3 PLLQ2 PLLQ1 PLLQ0
Reserv
ed
PLLSRC Res. Res. Res. Res. PLLP1 PLLP0
rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. PLLN PLLM5 PLLM4 PLLM3 PLLM2 PLLM1 PLLM0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bit 31 Reserved, must be kept at reset value.
Bits 30:28 PLLR: PLL division factor for I2S and System clocks
Set and cleared by software to control the clock frequency. These bits should be written only
if PLL is disabled.
clock frequency = VCO frequency / PLLR with 2 ≤ PLLR ≤
7
000: PLL = 0, wrong configuration
001: PLL = 1, wrong configuration
010: PLL = 2
...
111: PLL = 7
Bits 27:24 PLLQ: Main PLL (PLL) division factor for random number generator clocks
Set and cleared by software to control the frequency of the random number generator clock.
These bits should be written only if PLL is disabled.
0000: PLLQ = 0, wrong configuration
0001: PLLQ = 1, wrong configuration
0010: PLLQ = 2
0011: PLLQ = 3
0100: PLLQ = 4
...
1111: PLLQ = 15
Bit 23 Reserved, must be kept at reset value.
Bit 22 PLLSRC: Main PLL(PLL) entry clock source
Set and cleared by software to select PLL clock source. This bit can be written only when
the PLL is disabled.
0: HSI clock selected as PLL clock entry
1: HSE oscillator clock selected as PLL clock entry
Bits 21:18 Reserved, must be kept at reset value.
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