RM0401 Rev 3 41/771
RM0401
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2.3 Embedded SRAM
STM32F410 devices feature 32 Kbytes of system SRAM.
The embedded SRAM can be accessed as bytes, half-words (16 bits) or full words (32 bits).
Read and write operations are performed at CPU speed with 0 wait state.
The CPU can access the embedded SRAM1, through the System Bus or through the I-
Code/D-Code buses when boot from SRAM is selected or when physical remap is selected
(Section 7.2.1: SYSCFG memory remap register (SYSCFG_MEMRMP) in the SYSCFG
controller). To get the max performance on SRAM execution, physical remap should be
selected (boot or software selection).
2.4 Flash memory overview
The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash
memory. It implements the erase and program Flash memory operations and the read and
write protection mechanisms. It accelerates code execution with a system of instruction
prefetch and cache lines.
APB1
0x4000 7800 - 0x4000 FFFF Reserved
0x4000 7400 - 0x4000 77FF DAC
0x4000 7000 - 0x4000 73FF PWR
0x4000 6400 - 0x4000 6FFF Reserved
0x4000 6000 - 0x4000 63FF I2C4 FM+
0x4000 5C00 - 0x4000 5FFF Reserved
0x4000 5800 - 0x4000 5BFF I2C2
0x4000 5400 - 0x4000 57FF I2C1
0x4000 4800 - 0x4000 53FF Reserved
0x4000 4400 - 0x4000 47FF USART2
0x4000 3C00 - 0x4000 43FF Reserved
0x4000 3800 - 0x4000 3BFF SPI2 / I2S2
0x4000 3400 - 0x4000 37FF Reserved
0x4000 3000 - 0x4000 33FF IWDG
0x4000 2C00 - 0x4000 2FFF WWDG
0x4000 2800 - 0x4000 2BFF RTC & BKP Registers
0x4000 1400 - 0x4000 27FF Reserved
0x4000 1000 - 0x4000 13FF TIM6
0x4000 0C00 - 0x4000 0FFF TIM5
0x4000 0000 - 0x4000 0BFF Reserved
Table 1. Register boundary addresses (continued)
Bus Boundary address Peripheral
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