To Next Page

To Previous Page

RM0401 Rev 3 447/771

RM0401 Basic timers (TIM6)

449

17.4.4 TIM6 status register (TIMx_SR)

Address offset: 0x10

Reset value: 0x0000

17.4.5 TIM6 event generation register (TIMx_EGR)

Address offset: 0x14

Reset value: 0x0000

17.4.6 TIM6 counter (TIMx_CNT)

Address offset: 0x24

Reset value: 0x0000

1514131211109876543210

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. UIF

rc_w0

Bits 15:1 Reserved, must be kept at reset value.

Bit 0 UIF: Update interrupt flag

This bit is set by hardware on an update event. It is cleared by software.

0: No update occurred.

1: Update interrupt pending. This bit is set by hardware when the registers are updated:

– At overflow or underflow regarding the repetition counter value and if UDIS = 0 in the

TIMx_CR1 register.

– When CNT is reinitialized by software using the UG bit in the TIMx_EGR register, if URS = 0

and UDIS = 0 in the TIMx_CR1 register.

1514131211109876543210

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. UG

Bits 15:1 Reserved, must be kept at reset value.

Bit 0 UG: Update generation

This bit can be set by software, it is automatically cleared by hardware.

0: No action.

1: Re-initializes the timer counter and generates an update of the registers. Note that the

prescaler counter is cleared too (but the prescaler ratio is not affected).

1514131211109876543210

CNT[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 CNT[15:0]: Counter value

ST STM32F410 User Manual

Questions and Answers: