ST STM32F410 User Manual

RM0401 Rev 3 595/771
RM0401 Inter-integrated circuit (I
2
C) interface
626
The block diagram of the I
2
C interface is shown in Figure 208.
Figure 208. I
2
C block diagram
1. SMBA is an optional signal in SMBus mode. This signal is not applicable if SMBus is disabled.
23.3.2 I
2
C slave mode
By default the I
2
C interface operates in Slave mode. To switch from default Slave mode to
Master mode a Start condition generation is needed.
The peripheral input clock must be programmed in the I2C_CR2 register in order to
generate correct timings. The peripheral input clock frequency must be at least:
• 2 MHz in Sm mode
• 4 MHz in Fm mode
As soon as a start condition is detected, the address is received from the SDA line and sent
to the shift register. Then it is compared with the address of the interface (OAR1) and with
OAR2 (if ENDUAL=1) or the General Call address (if ENGC = 1).
$ATASHIFTREGISTER
#OMPARATOR
/WNADDRESSREGISTER
#LOCKCONTROL
3TATUSREGISTERS
#ONTROLREGISTERS
#ONTROL
#LOCK
CONTROL
$ATA
CONTROL
3#,
LOGIC
$UALADDRESSREGISTER
$ATAREGISTER
0%#REGISTER
)NTERRUPTS
0%#CALCULATION
3-"!
3$!
2EGISTER##2
3232
#2#2
$-!REQUESTS!#+
-36
.OISE
FILTER
.OISE
FILTER

ST STM32F410 Specifications

General

Brand	ST
Model	STM32F410
Category	Microcontrollers
Language	English